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657 Views
Registered: ‎10-15-2018

Spartan 6 XC6SLX45T, Integrated Block for PCI Express, v2.4, Register Read Fails

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Problem:

In the system specified below, the register read access fails if our add-in card is connected directly to the CPU (SLOT 2 ... 7, see System.jpg). If the card is in SLOT 1 (Intel PCH C621 Bridge), it works. Writing the registers seems to work for both. The behavior is new and only occurs with this system. Otherwise the add-in card runs stable in our series (>3k pieces).

What can be the cause of this wrongdoing?

System:

Add-In Card: Integrated Block for PCI Express v2.3, 32bit Address-Bars, 16k Range, Spartan 6 XC6SLX45T

OS: Windows 10, 64bit, Build 1903

CPU: Intel Xeon Gold 6246 CPU, RAM 96GB

SLOTS 1: PCIe x4 G3

SLOTS 2 ... 7: PCIe x8 G3

 
System.jpg
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288 Views
Registered: ‎10-15-2018

We found the problem and solved it. There was an incorrect LwrAdr generation in the completion header. The LwrAdr must be generated from the byte address. We used the 32bit address. This problem only arises at the CPU slots. The PCH slot is more tolerant here.

Failure scenario:

PCIE.JPG

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2 Replies
liy
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Are you able to check the  AER to see if it is  completion timeout or  rx rollover error when  read fails?

this will help to understand this issue .

and If the issue is only seen when you read the registers frequently? one difference between the slots seems to be the speed

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289 Views
Registered: ‎10-15-2018

We found the problem and solved it. There was an incorrect LwrAdr generation in the completion header. The LwrAdr must be generated from the byte address. We used the 32bit address. This problem only arises at the CPU slots. The PCH slot is more tolerant here.

Failure scenario:

PCIE.JPG

View solution in original post