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Adventurer
Adventurer
7,273 Views
Registered: ‎03-02-2010

Stalling a PCIe transmission

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Hi all,

 

I have some PCIe logic in the ML605 board which responds to PCIe memory r/w requests from a host PC. The thing is that during active transmission of a completion packet following a memory read request, I need to "stall" the transmission at least once. Based on my understanding, my logic is suppose to present [new] 64 bits of data on every positive trn_clk edge after trn_tsof_n is asserted. My FSM is as such that at least once, the same data is presented for two trn_clk cycles. Would de-asserting trn_tsrc_rdy_n for one of the two trn_clk cycles fit the requirement of new data on trn_td for every positive edge of trn_clk?

 

Thanks

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Voyager
Voyager
11,034 Views
Registered: ‎04-02-2011

Re: Stalling a PCIe transmission

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Voyager
Voyager
7,270 Views
Registered: ‎04-02-2011

Re: Stalling a PCIe transmission

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I have some PCIe logic in the ML605 board which responds to PCIe memory r/w requests from a host PC. The thing is that during active transmission of a completion packet following a memory read request, I need to "stall" the transmission at least once.

 


 

 

What do you mean "I need to "stall" the transmission at least once". ?

 

if you want to stop the PCIe Xansmission according to your custom requirement you should handle the TX & RX Statemachines very well according to custom your requirement.But the same may not work well coz it may hang-up at the run time.

The Best way will be to inform the root complex whenever you want to stop the write from Ednpoint side.

 

 


 

 

Based on my understanding, my logic is suppose to present [new] 64 bits of data on every positive trn_clk edge after trn_tsof_n is asserted.

 


 

This is  correct!

 

 


 

My FSM is as such that at least once, the same data is presented for two trn_clk cycles. Would de-asserting trn_tsrc_rdy_n for one of the two trn_clk cycles fit the requirement of new data on trn_td for every positive edge of trn_clk?

 


 

Most Probably should work!

 

What is your user interface data width from your custom logic 8-bit/16-bit or 32 bit ?

 

Based on that you should write your own custom FSM/(custom logic) to convert the incoming data into required (64-bit) for the TX engine to allow Xansmission occur successfully with PCIe bus with your RootComplex.

 

Explain a bit more in more comprehensive format to help you better.


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Adventurer
Adventurer
7,239 Views
Registered: ‎03-02-2010

Re: Stalling a PCIe transmission

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Thanks 

 

 

 

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Voyager
Voyager
11,035 Views
Registered: ‎04-02-2011

Re: Stalling a PCIe transmission

Jump to solution

 


 

 

 

 


 

 

 

 

 

 

 

 

 

 

 

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