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Visitor ramiby
Visitor
1,389 Views
Registered: ‎12-26-2018

Streaming XDMA writeback problem

Shalom.

I'm Using

  • Card - VCU-118 Evaluation platform with VIVADO 2017.3
  • Host - Intel with vxWorks 6.9

I succeeded to run streaming c2h and loopback (h2c2h) in polling mode but no writing was done to the writeback address.

My driver setting:

  • 'Channel Interrupt Enable' sets to 0  (all fields)
  • Descriptor list with one element sets to 'pollmode wb addr' with 'Stop' and 'EOP' set to 1
  • Channel control with 'ie descriptor completed' and 'pollmode wb enable' set to 1

The result:

  • All the required data was copied to the Host by the XDMA
  • Channel Completed Descriptor Count is 1 as expected
  • no writing was done to the writeback address

What I missed please?

Thanks for any help.

 

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14 Replies
Moderator
Moderator
1,331 Views
Registered: ‎02-16-2010

Re: Streaming XDMA writeback problem

@ramiby

Can you read the following registers to confirm if the writeback address is set correctly?

H2C Poll Mode Low Write Back Address (0x88) -- offset 0x0088

H2C Poll Mode High Write Back Address (0x8C) -- offset 0x008C

C2H Poll Mode Low Write Back Address (0x88) -- offset 0x1088

C2H Poll Mode High Write Back Address (0x8C) -- offset 0x108C

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Participant jsara
Participant
1,236 Views
Registered: ‎08-14-2015

Re: Streaming XDMA writeback problem

I have the same problem.  I have verified that the write back buffer is set, as well as bits 2 and 26 in the ie register (to enable writeback).

 

Does writeback work when using descriptor bypass, which is how we are running?

 

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Visitor ramiby
Visitor
1,205 Views
Registered: ‎12-26-2018

Re: Streaming XDMA writeback problem

The writeback address is set correctly:

C2H Poll Mode Low Write Back Address (0x88)   -- offset 0x1088 = 0x424BF800

C2H Poll Mode High Write Back Address (0x8C) -- offset 0x108C = 0x00000000

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Participant jsara
Participant
1,194 Views
Registered: ‎08-14-2015

Re: Streaming XDMA writeback problem

Yes, I have verified that the write back is set correctly as per the prior post.  In fact XDMA initializes the write back buffer, even when not in POLL_MODE.  I have tried both the drivers initial buffer and the one I allocated in a new ioctl call of the modified driver.  The buffer value never gets changed.  And I know that I have the physical address sent to the 0x1088 (low 32 bits) and 0x108c (high 32 bits) and that it matches my virtual address because I can write the same locations and see changes successfully using the descriptor bypass on the c2h channel.

IS THE WRITEBACK verified to be working?  Is it known to work with descriptor bypass?  Is it know to work with Artix 7 parts?

Note that when I set POLL_MODE to 1 in the registry the original simpledma.c code does not return any data (even before I changed over to descriptor bypass mode).  This is another indication that write back does not work, at least for me.

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Contributor
Contributor
1,050 Views
Registered: ‎06-27-2016

Re: Streaming XDMA writeback problem

Has anyone solved this? I am having the same problem with xdma streaming C2H writeback not working. I'm using Vivado 2018.2.

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Participant jsara
Participant
1,040 Views
Registered: ‎08-14-2015

Re: Streaming XDMA writeback problem

It is disappointing how poor Xilinx support is at addressing problems.  Regardless, I have a solution: DO NOT USE WRITEBACK, IT DOES NOT WORK.  I do have descriptor bypass working in the firmware.  What this means is that I can write to anywhere in host memory (just like a writeback of DMA completed does).  This also means that you can implement your own writeback in the firmware, and you can do a better job because you and define your own structure to write back, providing more info that the predefined writeback.  Does that help?

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Participant jsara
Participant
1,039 Views
Registered: ‎08-14-2015

Re: Streaming XDMA writeback problem

Just be be redundant.  Assume that writeback does not work and never will.

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Contributor
Contributor
984 Views
Registered: ‎06-27-2016

Re: Streaming XDMA writeback problem

Is this discussion in error? It seems to say writeback is successful (user errored tkeep setting in custom code.)

https://forums.xilinx.com/t5/PCI-Express/XMDA-C2H-Stream-writeback-with-wrong-Length-field/td-p/908685

 

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Participant jsara
Participant
977 Views
Registered: ‎08-14-2015

Re: Streaming XDMA writeback problem

I can only pray that someone from Xilinx will monitor this formum and answer this question.  I have not seen any such support in the past 3 years of using this forum.

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Contributor
Contributor
945 Views
Registered: ‎06-27-2016

Re: Streaming XDMA writeback problem

@ramiby I solved a similar problem in my driver by noticing PG195 Table 2-5: Descriptor Fields where it says the Src_adr must be set to the "Metadata writeback address for C2H transfer".

I had missed this and was only setting up the C2H Poll Mode Write Back Addresses.

Setting the C2H Src_adr with the write-back address can also be seen in the xdma driver libxdma.c xdma_cyclic_transfer_setup function code : 

/* replace source addresses with result write-back addresses */
memset(engine->cyclic_result, 0,
CYCLIC_RX_PAGES_MAX * sizeof(struct xdma_result));
bus = engine->cyclic_result_bus;
for (i = 0; i < xfer->desc_num; i++) {
xfer->desc_virt[i].src_addr_lo = cpu_to_le32(PCI_DMA_L(bus));
xfer->desc_virt[i].src_addr_hi = cpu_to_le32(PCI_DMA_H(bus));
bus += sizeof(struct xdma_result);
}

I am still not seeing the Magic value for some reason, but EOP and Length, which I am primarily interested in for my network streaming application, are correct.

Hope this helps you. 

Participant jsara
Participant
938 Views
Registered: ‎08-14-2015

Re: Streaming XDMA writeback problem

This does not sound correct.  If this is how write back should be done then Xilinx needs to correct their documentation.  Write back values should be writted to a write back address, not a generic dma source address !!!

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Contributor
Contributor
934 Views
Registered: ‎06-27-2016

Re: Streaming XDMA writeback problem

To complete my discoveries. I was not seeing C2H Magic due to my setting of the C2H Poll Mode Write Back Address.

When using C2H streaming with interrupts - and NOT doing poll mode - the Poll Mode Write Back should NOT be set. Because I had mistakenly set both C2H descriptor Src_adr and the C2H Poll Mode WB, the xdma engine was overwriting the WB address with poll mode values AFTER C2H streaming had set the same address with correct metadata (Magic/EOP).

My driver now works as expected for C2H streaming interrupt mode - by setting ONLY the C2H descriptor Src_adr to a write-back address on the host, with NO setting of any Poll Mode address in the xdma engine.

My only defence in this is that perhaps the documentation is less than clear about "Write Back" methods for C2H poll/interrupt modes and it is easy for beginners to confuse the two.

Contributor
Contributor
933 Views
Registered: ‎06-27-2016

Re: Streaming XDMA writeback problem

@jsara Agreed, the documentation needs clarification on this!
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Moderator
Moderator
902 Views
Registered: ‎02-11-2014

Re: Streaming XDMA writeback problem

Hello @jsara,

I have filed a Change Request to get PG195 information on C2H streaming write-back and Poll mode write-back clarified with @lander60654's findings.

Thanks,
Cory

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