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tomturbo
Observer
Observer
342 Views
Registered: ‎02-06-2014

Swap PCIe Pins in Vivado 2019.1

I have got an Artix Board with PCIe lines not connected in the correct ordering.

When I wanted to change the PCIe lines in Vivado, I ran into a problem:

 

I can assign the corret location in the tools. ("Open synthisized design") The tools seem to move the pins correctly. (When I assign the TX lines, the corresponding RX lines move as well) But the new locations are not used in P&R. The new locations are not even saved in the constraints file.

When I enter the locations manually in the constraints file, I get an error when opening the synthisized design. ("Location already in use")

The assignment of the other FPGA pins work just fine.

 

What to do? I have to use this board unfortunately.

BTW I am using the xdma demo design.

 

 

 

 

 

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2 Replies
mmcnicho
Xilinx Employee
Xilinx Employee
223 Views
Registered: ‎10-09-2019

Hi,

I want to make sure I understand your issue.

Is the lane width x1? Are you trying to swap the Tx and Rx pins?

Thanks!

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tomturbo
Observer
Observer
203 Views
Registered: ‎02-06-2014

It is a x4 design.

The position of the rx and tx pins on the board are not where Vivado wants them to be.

But I figured it out in the mean time looking at an example design:

The constraints for rx and tx have to be put in a different .xdc file. The property "processing_order" of this file has to be set to "early".

 

Now it is working.  At least I get a correct bit file, but Vivado still complaints when I open synthisized or implemented design.

 

I still yould like to know why this is the case. Is this a bug or is it a feature? Am I doing it all wrong?

 

 

 

 

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