01-10-2021 01:49 AM
I have got an Artix Board with PCIe lines not connected in the correct ordering.
When I wanted to change the PCIe lines in Vivado, I ran into a problem:
I can assign the corret location in the tools. ("Open synthisized design") The tools seem to move the pins correctly. (When I assign the TX lines, the corresponding RX lines move as well) But the new locations are not used in P&R. The new locations are not even saved in the constraints file.
When I enter the locations manually in the constraints file, I get an error when opening the synthisized design. ("Location already in use")
The assignment of the other FPGA pins work just fine.
What to do? I have to use this board unfortunately.
BTW I am using the xdma demo design.
01-21-2021 01:56 AM - edited 01-21-2021 01:58 AM
It is a x4 design.
The position of the rx and tx pins on the board are not where Vivado wants them to be.
But I figured it out in the mean time looking at an example design:
The constraints for rx and tx have to be put in a different .xdc file. The property "processing_order" of this file has to be set to "early".
Now it is working. At least I get a correct bit file, but Vivado still complaints when I open synthisized or implemented design.
I still yould like to know why this is the case. Is this a bug or is it a feature? Am I doing it all wrong?