Does anybody take such situation:
while active l0_legacy_int_funct0 and extracting memory read pkt from the RX buffer integrated block sets synchronous llk_rx_sofn and llk_rx_eof_n signals
in the same cycle, without significiant data, then sets valid signals with valid data (see attached file).
That does it mean, who knows?
Were you able to get to the bottom of this?
I'm curious on what caused this.