03-06-2020 02:23 AM
I'm trying to understand the correct timing of TLAST and TVALID when connected to a C2H stream of the DMA/Bridge subsystem for PCI express 4.1 (XDMA). I am trying to keep it as simple as possible. I have a AXI Stream master peripheral which simply counts pulses. The data is streamed in to the the C2H of the XDMA. Both AXI Master and slave are set to 64 bit wide ("words") If I assert the TLAST when word count is less than 8, I have no problem all 8*64 or 64 bytes arrive at the host. But if I increase word count above this number the driver just hangs. I am keeping TSRB and TKEEP all 1s as everything is alligned to word boundries (I think)
If I use an ILA to look at the signals, I note that TREADY is going low every 128 clock cycles. I tried to match this by asserting TVALID low and then immedietly high again. I am not sure if TVALID ever needs to change, can I safely hold it high always? I don't understand how I am supposed to signal the end of transmission except by TLAST. The driver is set to poll mode, but I assumed the DMA engine writes into the register the number of bytes transfered, or do I have to do something on a side band channel to tell it this? Why does this magic 64 bytes work - is it one TLP packet, and when I go over the packet boundary, I have to do something else? TLAST is normally an end of packet marker, but then how do I do end of transmission? Just to be clear I am using the latest driver on Linux and use the dma_from_device tool (I also tried dd) with the size set to my transmission size (e.g. 8 bytes, or 1024 or other larger sizes)
I've read the manual carefully, and apart from being ambigious about TLAST (end of packet or end of transmisison) I can not see anything in there to help. Other forum posts alluded to cyclic buffers being turned off (how do I do that?) and setting TSTRB to something else (What? When?)
I would be very greateful for some help as I am sure this is something quite simple. Connecting C2H stream to H2C stream lines works as per the Xilinx example, but it shouldn't really as TVALID should be set before TREADY. Presumably TLAST goes high on every TLAST coming in but when does that occur? For that test any number of bytes can be transfered, and there is no TSTRB, TKEEP or side band communication.
Thank you in advance.
03-09-2020 03:18 AM
For comparison, I have included the ILA waveforms for the Xilinx reference design using a loop back between C2H and H2C. As you can see, my timing is the same, so I can't understand why the loop back works, but just adding in a simple RTL counter with the same handshaking doesn't work. Grateful for any input.