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Visitor
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Registered: ‎03-24-2015

TLP prefix support of UltraScale+ Devices Block for PCIe v1.3

Hi PCIe experts,

I want to implement TLP prefix with "UltraScale+ Devices Block for PCIe v1.3" but I found that it doesn't support the feature.

But I found that 7 series support it which is described in "ug477_7Series_IntBlock_PCIe.pdf".

So,  can you give me any suggestion how to impement the TLP prefix with Xilinx IP.

What I can think about is to do it in the ways below,

1. Modify IP of UltraScale+ Devices Block for PCIe v1.3. Is it possible?

2. Implement the design with PCIE PHY only. With this way, I need to implement the whole PCIe controller. Seems too difficult.

Any other options?

 

Thanks,

Clarke

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Visitor
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Registered: ‎03-24-2015

I found QDMA IP has PASID feature.

https://github.com/Xilinx/dma_ip_drivers/blob/master/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c

The PASID can only send with TLP prefix. And QDMA IP is based on PCIe integrated Block IP. So, I think there is still a way to send TLP prefix with the PCIe integrated block IP. Xilinx just didn't expose the interface or didn't describe the feature in the IP document.

Can anyone from Xilinx can give some suggestions?

Thanks,

Clarke

 

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