cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sumaiya
Adventurer
Adventurer
559 Views
Registered: ‎10-29-2017

Tandem PCIe with field updates doesn't generate <project_name_partial.bit>, <project_name_partial_clear.bit> files in Zynq US+ devices

Jump to solution

Hi, 

   I'm targeting on PCIe IP enabling 'Tandem PCIe with field updates' in Zynq XCZU19EG.

   Initially, I generated example design in KCU105 enabling 'Tandem PCIe with field updates' and bitstreams are generated successfully. Generated bitstream files are

1. ver1_tandem1.bit

2. ver1_tandem2.bit

3. ver1_partial.bit

4. ver1_partial_clear.bit 

    According to the procedure of this feature, partial and partial_clear bit files are mandatory to update the fields.

     When I tried to generate bitstream for example design in ZCU104 EV, partial.bit and partial_clear.bit are not generated. Are these bit files not required for Zynq? or Do we need to modify generate_bitstreams.tcl in such a way to generate partial.bit and partial_clear.bit files manually? 

    If those files are not required in zynq devices, then what is the procedure to update fields in Tandem PCIe. 

    Please clarify the query. 

0 Kudos
1 Solution

Accepted Solutions
garethc
Moderator
Moderator
547 Views
Registered: ‎06-29-2011

Hi @sumaiya 

Removal of the cleaing bitstreams is not related to Zynq specificatlly but is for all Ultrascale+. This is because clearing bitstreams are not required as they are not necessary for PR in Ultrascale+.

Thanks,

Gareth


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
3 Replies
garethc
Moderator
Moderator
548 Views
Registered: ‎06-29-2011

Hi @sumaiya 

Removal of the cleaing bitstreams is not related to Zynq specificatlly but is for all Ultrascale+. This is because clearing bitstreams are not required as they are not necessary for PR in Ultrascale+.

Thanks,

Gareth


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
sumaiya
Adventurer
Adventurer
523 Views
Registered: ‎10-29-2017

Hi @garethc ,

    Thanks for your response. 

    What about partial bitstream files? In generate_bitstream.tcl, no_partial_bitstream is used. So, Partial bitstream files are not generated automatically. Whereas if we remove that and try, partial bitstream files are being generated. 

    So, to have partial bitstream file, we need to edit tcl script manually? Is it a right way to do? 

    One more query is to load ver1 and ver2 bit files through PCIe link, the procedure remains same as showed in 'Tandem PCIe with field updates using KCU105'? Is there any difference between kintex and zynq? 

     Please calrify. 

0 Kudos
garethc
Moderator
Moderator
453 Views
Registered: ‎06-29-2011

Hi @sumaiya 

With US+ partial bitstreams are not required as stage 2 bitstreeams can be used as partial bitstreams in the US+ Field Updatessolution. I recommend that you read through PG213 Tandem With Field Updates section from Page 99 including the Bitstream Generation section from Page 104. This should answer all your questions.

Thanks,

Gareth


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------
0 Kudos