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pangwenbin
Observer
Observer
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Registered: ‎07-10-2018

Tandem XDMA Issue

I am trying design PCIE gen3 with XDMA IP Core which option Tandem is selected.If the design is an example provided buyvivado2017.4,the implementation pass and generate bitfile.BUT i add "mark_debug="true"" to the design,the implementation failure.The error message is:

[DRC HDTC-12] CONFIG cells must be in stage one: Configuration cell 'dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst' is not marked as a stage 1 cell. This cell must be added to stage 1 or removed from your design. You may also need to add additional driving logic to stage 1 as dictated by the desired design behavior. To add this cell to stage 1, please do the following:
set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst]

 

AND i am not clear which cells should be include in stage 1.SO how to move some cells or my app logic into stage 1?

Thanks for any help.

Wenb Pang

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venkata
Moderator
Moderator
858 Views
Registered: ‎02-16-2010

https://forums.xilinx.com/t5/PCI-Express/xdma-tandem-help-me/td-p/883140
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