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mmatusov
Voyager
Voyager
535 Views
Registered: ‎02-17-2009

Tight setup and hold pins in XDMA

I can see that the tools struggle with some paths inside of the XDMA core. Please see attached report on the tight setup and hold pins. I was wondering if there is a missing multicycle constraint? Here is a schematic for one of these paths:Screenshot - 2020-03-09 , 5_44_09 PM.png

Both clocks are based on the same CLK_TXOUTCLK:

Screenshot - 2020-03-09 , 5_50_08 PM.png

Thanks,
/Mikhail

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garethc
Moderator
Moderator
493 Views
Registered: ‎06-29-2011

Hi @mmatusov 

When creating a post can you please provide more details.

e.g. Note: When initiating a forum post, please don’t forget to mention the following details at the start: 

  • Vivado Version (e.g. 2018.2, 2019.2 etc.)
  • Name of the IP (e.g. UltraScale+ Devices Integrated Block for PCI Express, DMA/Bridge Subsystem for PCI Express (Bridge Mode), DMA/Bridge Subsystem for PCI Express (DMA mode) etc.)
  • Device Family (e.g. Virtex Ultrascale+, Kintex Ultrascale etc.)

This is detailed in the PCIe and CPM Board - Useful Resources sticky post that is seen at the top of the board when you are on it. You should always review this before posting and below is a link to it.
https://forums.xilinx.com/t5/PCIe-and-CPM/PCIE-and-CPM-Useful-Resources/m-p/1079558/highlight/true#M15894

Regarding your observation that there is tight setup and hold on these pins

  • Do you see an error or is this failing timing?
  • What version of the tools are you using and have you tried with the most recent version and the example design?
Thanks,

Gareth


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mmatusov
Voyager
Voyager
475 Views
Registered: ‎02-17-2009

My apologies for not providing the full information:

  • Vivado Version - 2019.2
  • Name of the IP - DMA/Bridge Subsystem for PCI Express (DMA mode)
  • Device Family - Zynq UltraScale+ RFSoC

No, this doesn't result in an error or failing timing however this seems to affect timing closure of my bigger design. The tools I am using are the latest.

I haven't checked this in an example design. I am not sure if I will see this when implementing in an otherwise empty device but I will try it.

Thanks,
/Mikhail

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mmatusov
Voyager
Voyager
456 Views
Registered: ‎02-17-2009

I tried building the example design. I don't see the same tight setup and hold pins but I do see a number of critical timing warnings in the methodology report such as the following:

TIMING #1 Critical Warning A primary clock xdma_1_i/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/xdma_1_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.xdma_1_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK is created on the output pin or net xdma_1_i/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/xdma_1_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.xdma_1_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK of a Clock Modifying Block

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