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tlstkdtjq
Visitor
Visitor
3,098 Views
Registered: ‎05-29-2011

Translate XAPP1052 Design to VHDL, need some equivalence statements

Hi,

i would like to translate the BMD Design to VHDL. Some statements are not clear to translate,can someone help me ?

 

 

wire  [2:0]         mwr_func_num = (!mwr_phant_func_dis1_i && cfg_phant_func_en_i) ? 
                                       ((cfg_phant_func_supported_i == 2'b00) ? 3'b000 : 
                                        (cfg_phant_func_supported_i == 2'b01) ? {cur_wr_count[8], 2'b00} : 
                                        (cfg_phant_func_supported_i == 2'b10) ? {cur_wr_count[9:8], 1'b0} : 
                                        (cfg_phant_func_supported_i == 2'b11) ? {cur_wr_count[10:8]} : 3'b000) : 3'b000;

 

 

Has anyone also translated the example design ?

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luisb
Xilinx Employee
Xilinx Employee
3,075 Views
Registered: ‎04-06-2010

This is basically just a big nested if-else statement.  It happens to be at the declaration of the wire, but it could easily have been done elsewhere.  

 

Below is an equivalent: 

 

Verilog:

assign <output> = <condition> ? <input1> : <input0>;

 

VHDL:

   if <condition> then     

<output>   <= <input1>;

   else  

<output>   <= <input0>

   end if;

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