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avinashc
Explorer
Explorer
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Registered: ‎10-09-2018

Trouble implementing XDMA -XAPP1052 in ISE 14.7

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Hello,

I am having trouble implementing DMA -BMD design setup on Spatan 6 board in ise 14.7

setup- Win 10 - 64 bit, ISE 14.7

I have generated PCIe ip core for sparatan 6 board and generated bit file in project. Following that extracted xapp1052.zip in specified location as per xapp 1052.pdf(pg9) and put .prj file in implement folder and ucf and scr file in resp. folder.

After that, i ran xilperl command and got following error.

Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -aul
-verbose -uc
E:/Xilinx_ISE_DS_Win_14.7_1015_1/projects/bmd_design2/ipcore_dir/bmd_design/dma_
performance_demo/fpga/implement\ucf/xilinx_pcie_1_lane_ep_xc6slx100t-fgg484-3.uc
f -sd
E:/Xilinx_ISE_DS_Win_14.7_1015_1/projects/bmd_design2/ipcore_dir/bmd_design/dma_
performance_demo/fpga/implement\..\..\..\..\
E:/Xilinx_ISE_DS_Win_14.7_1015_1/projects/bmd_design2/ipcore_dir/bmd_design/dma_
performance_demo/fpga/implement\results\xilinx_pci_exp_ep_top.ngc

WARNING:NgdBuild:257 - Launcher: Could not find the file
   "E:\Xilinx_ISE_DS_Win_14.7_1015_1\projects\bmd_design2\ipcore_dir\bmd_design\
   dma_performance_demo\fpga\implement\results\xilinx_pci_exp_ep_top" with
   extension "ngc" in the search path.
ERROR:NgdBuild:1364 - Top-level input design file
   "E:/Xilinx_ISE_DS_Win_14.7_1015_1/projects/bmd_design2/ipcore_dir/bmd_design/
   dma_performance_demo/fpga/implement/results/xilinx_pci_exp_ep_top.ngc" cannot
   be found or created. Please make sure the source file exists and is of a
   recognized netlist format (e.g., ngo, ngc, edif, edn, or edf).
Total REAL time to NGDBUILD completion:  1 sec
Total CPU time to NGDBUILD completion:   1 sec

Writing NGDBUILD log file "xilinx_pci_exp_ep_top.bld"...
ERROR: NGDBUILD completed with errors.
     : Implement_dma Terminating!

language is verilog.

I am seeing 1 ngc file but name in script is diff. than what is here, is that can be the problem?

ngc.jpg

What can be issue here, what other things i should take care?

Can anyone tell me exact flow w.r.t. my setup?

@liy @ebrahimm @bethe @kurihara 

Thanks!

Avinash

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Accepted Solutions
kurihara
Xilinx Employee
Xilinx Employee
879 Views
Registered: ‎07-26-2012

-top specify the name of top module of the design and -ofn is used for output file of the synthsized design. The error was looking for the output file and couldn't find it. So, it is needed to match the name between outputted file name from xst and ngdbuild input file name in the script.

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16 Replies
kurihara
Xilinx Employee
Xilinx Employee
1,230 Views
Registered: ‎07-26-2012

Did XST synthesizing go well? Was the NGC generatead without error? The script may have the top module name.

 

However, the app note is older and it could have any problem.

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avinashc
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Registered: ‎10-09-2018

hello @kurihara ,

synthesizing went well--no error..some warnings are there.

No timing or any error are present in the design.

so app note means xapp file you are referring to,right?

What can be done now,is there anything that i can change or look for like path,source file locations etc.?

I have added my project(incase if you want to check thorough).

 

Thanks!

 

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kurihara
Xilinx Employee
Xilinx Employee
1,205 Views
Registered: ‎07-26-2012

Your project has PIO design with bmd_design. PIO is another design. So I think the two designs will cause a bus collision. We recommend that you do a simulation.

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avinashc
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Registered: ‎10-09-2018

Hello @kurihara ,

I think as per xapp 1052 guide, I can use PIO  design in this,right?

I have just created IP core and used those files as it is, i haven't changed anything in that.I have used example design files  and generated bit file. Just did simulation that is also fine.

bmd_sim.jpg

Can you tell me in little brief, what I am doing wrong?

 

Thanks!

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avinashc
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Explorer
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Registered: ‎10-09-2018

Hello @kurihara ,

I am still stucked at this problem.

Can anyone tell me what to look for?

 

Thanks!

Avinash

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kurihara
Xilinx Employee
Xilinx Employee
1,106 Views
Registered: ‎07-26-2012

S6 design seems to use PIO. I referred to the 7 series design structure. I apologize.

Implement.sh has the following code and top file will be renamed:

mv xilinx_pcie_1_1_ep_s6.ngc ./results/s6_pcie_v2_4_top.ngc

 

Actually my running of implment.sh was completed successfully.

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "routed.bit".
Bitstream generation is complete.

avinashc
Explorer
Explorer
1,095 Views
Registered: ‎10-09-2018

Hello @kurihara ,

did you check with my project setup or yours? I have shared my project in this thread.

In my project implement.sh has the different code

mv xilinx_pcie_1_1_ep_s6.ngc ./results/bmd_design_top.ngc

running command"implement.bat" on command prompt works,even routed.bit file generates, but "xilperl implement_dma.pl" command not works as i have to implement it for DMA.

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avinashc
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Registered: ‎10-09-2018

Hello @kurihara 

I did not get any solution yet,what can be the reason for above problem?

 

Avinash

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kurihara
Xilinx Employee
Xilinx Employee
981 Views
Registered: ‎07-26-2012

When you see BMD design top file, BMD.v, it shows TRN interface is used. So, the PCIe IP also needs TRN interface which is version 1.4.

Then, the example design top file needs to change to include the IP core and BMD design. And also .xst file and scr file has to be matched with this.

Unfortunately, it is not updated becasue this is the old example file.

avinashc
Explorer
Explorer
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Registered: ‎10-09-2018

Hello @kurihara ,

I even tried with ip  core 1.4,not worked..same error.

Do i need to add all those bmd_design files in xilinx project and then synthesize it?

 

So which are my options to get spartan 6 pio design to work in burst payload option in ise14.7?

What can i do to get this design work in dma mode or multiple payload transfer mode?

 

Avinash

 

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kurihara
Xilinx Employee
Xilinx Employee
954 Views
Registered: ‎07-26-2012

The attached file does not have an error although 3 timing constraits are not met.

avinashc
Explorer
Explorer
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Registered: ‎10-09-2018

Hello @kurihara ,

I checked above project and noticed it has different project specs xc6slx45t with -2 speed...but my project has 100t with -3, so i changed that and again the same error is coming

i.e. ngdbuild-1364 ..as i have mentioned earlier.

 

About the changes you said to make in BMD  design, what are exact those?

can you recommend me some guide to explore how BMD  design exactly work, i want to know about packet formation difference in normal PIO design and BMD design.

 

Thanks! 

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kurihara
Xilinx Employee
Xilinx Employee
911 Views
Registered: ‎07-26-2012

For 100t-3, xst and scr files have to be changed to the part. And also, in ucf file there is RPM LOC property and it can cause placement error. So, please remove it and reconsider the placement to fit your design.

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avinashc
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Registered: ‎10-09-2018

Hello @kurihara ,

Yes,i also got those constraint error with xapp 1052's scr and ucf file.

In my project there is little bit difference wrt xapp note,i have attached jpeg below,please see itscr and xst.jpg

as you can see, my xst.scr file has diff -ifn name file wrt appnote scr file

name in -ofn amd -top file are different in app note project,but not in my,so does that can make error ngdbuild 1364?

 

thanks!

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kurihara
Xilinx Employee
Xilinx Employee
880 Views
Registered: ‎07-26-2012

-top specify the name of top module of the design and -ofn is used for output file of the synthsized design. The error was looking for the output file and couldn't find it. So, it is needed to match the name between outputted file name from xst and ngdbuild input file name in the script.

View solution in original post

avinashc
Explorer
Explorer
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Registered: ‎10-09-2018

Hello @kurihara ,

That was the problem,in -ofn file name was different in my scr file and it was searching for diff. name in script.

I changed that and it is working fine now with no constraint error.

Thank you for all the assistance.

I have 1 question-

(xapp 1052 provides driver and application, could that work in 64 bit-win10 or ubuntu system?

if it can't, what are the ways to get it work in 64 bit system?)

 

Avinash

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