UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor chickenjohn
Visitor
514 Views
Registered: ‎08-07-2017

Two MSI-X interrupts triggers same interrupt handler on VCU118

Hello,

I have a design with MSI-X capability. There are two interrupt sources in hardware. On the VCU118 board, both of them trigger the same interrupt handler in the driver at x86 host side. On NetFPGA-SUME board there is no such problem and interrupts work fine.

The design has a DMA/Bridge PCIe Subsystem IP. It is set to be Bridge mode. The design is developed using Vivado 2018.1 with AR71169 and AR71167 patched. The MSI-X vector table and PBA are assigned to BAR[3:2](64-bit address). The BAR is 128K and is only used by MSI-X structures. Two interrupt sources are concatenated and connected to usr_irq_req[1:0].

The driver enables MSI-X by pci_enable_msix_range(); A msix_entry structure is initialized, and two different request handlers are assigned to two interrupts respectively by request_irq(); There is no other operations about MSI-X in the driver side.

Thank you in advance for any suggestion.

Tags (2)
0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
441 Views
Registered: ‎12-10-2013

Re: Two MSI-X interrupts triggers same interrupt handler on VCU118

Hi @chickenjohn,

 

Could you provide an LSPCI -vvv of the Xilinx device, and ensure that your usr_irq lines are correctly mapped in the Register mapping of the Bridge?

 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos