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Visitor
Visitor
8,018 Views
Registered: ‎11-21-2009

UCF "ERROR:Pack:1107" !!! (xapp1052)

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As we know, we should conecct all ports in top module in the our project to the FPGA Pins in ucf, here :

Top moudul is:

module xilinx_pci_exp_ep (
  // PCI Express Fabric Interface

  pci_exp_txp, //---> (0:7)
  pci_exp_txn, //---> (0:7)
  pci_exp_rxp, //---> (0:7)
  pci_exp_rxn, //---> (0:7)
  // System (SYS) Interface
  sys_clk_p,
  sys_clk_n,
  sys_reset_n,
  refclkout
  );//synthesis syn_noclockbuf=1



According to the user guid (ML555-ug201.pdf) we can see :
PETP0 W1  
PETN0 Y1
PERP0 V2
PERN0 W2
PETP1 AB1
PETN1 AA1
PERP1 AC2
PERN1 AB2
PETP2 AE1
..
..
..
..
..
And I wrote like bellow in the UCF file in order to conect all ports to the FPGA pins:

#*** PCIe Receiver Interface  
NET "pci_exp_txp<0>" LOC ="W1";
NET "pci_exp_txn<0>" LOC ="Y1";  
NET "pci_exp_txp<1>" LOC ="AB1";
NET "pci_exp_txn<1>" LOC ="AA1";
NET "pci_exp_txp<2>" LOC ="AE1";
NET "pci_exp_txn<2>" LOC ="AF1";
NET "pci_exp_txp<3>" LOC ="AH1";
NET "pci_exp_txn<3>" LOC ="AG1";
NET "pci_exp_txp<4>" LOC ="N1";
NET "pci_exp_txn<4>" LOC ="P1";
NET "pci_exp_txp<5>" LOC ="T1";
NET "pci_exp_txn<5>" LOC ="R1";
NET "pci_exp_txp<6>" LOC ="AL1";
NET "pci_exp_txn<6>" LOC ="AM1";
NET "pci_exp_txp<7>" LOC ="AP3";
NET "pci_exp_txn<7>" LOC ="AP2";

#*** PCIe Transmitter Interface
NET "pci_exp_rxp<0>" LOC ="V2";
NET "pci_exp_rxn<0>" LOC ="W2";
NET "pci_exp_rxp<1>" LOC ="AC2";
NET "pci_exp_rxn<1>" LOC ="AB2";
NET "pci_exp_rxp<2>" LOC ="AD2";
NET "pci_exp_rxn<2>" LOC ="AE2";
NET "pci_exp_rxp<3>" LOC ="AJ2";
NET "pci_exp_rxn<3>" LOC ="AH2";
NET "pci_exp_rxp<4>" LOC ="M2";
NET "pci_exp_rxn<4>" LOC ="N2";
NET "pci_exp_rxp<5>" LOC ="U2";
NET "pci_exp_rxn<5>" LOC ="T2";
NET "pci_exp_rxp<6>" LOC ="AK2";
NET "pci_exp_rxn<6>" LOC ="AL2";
NET "pci_exp_rxp<7>" LOC ="AN4";
NET "pci_exp_rxn<7>" LOC ="AN3";.
..
..
..
..
..
..

But I faced errors as bellow:




ERROR:Pack:1107 - Unable to combine the following symbols into a single IPAD component: BUF symbol "pci_exp_rxn_0_IBUF" (Output Signal = pci_exp_rxn_0_IBUF)
  PAD symbol "pci_exp_rxn<0>" (Pad Signal = pci_exp_rxn<0>)
  An IO component of type IPAD was chosen because the IO contains symbols
  and/or properties consistent with input usage and also connected directly to
  a Black Box symbol.
  Each of the following constraints specifies an illegal physical site for a
  component of type IPAD:
  Symbol "pci_exp_rxn<0>" (LOC=W2 [Physical Site Type = OPAD])
  The component type is determined by the types of logic and the properties and
  configuration of the logic it contains. Please double check that the types of
  logic elements and all of their relevant properties and configuration options
  are compatible with the physical site type of the constraint.

ERROR:Pack:1107 - Unable to combine the following symbols into a single IPAD component: BUF symbol "pci_exp_rxn_1_IBUF" (Output Signal = pci_exp_rxn_1_IBUF)
  PAD symbol "pci_exp_rxn<1>" (Pad Signal = pci_exp_rxn<1>)
  An IO component of type IPAD was chosen because the IO contains symbols
  and/or properties consistent with input usage and also connected directly to
  a Black Box symbol.
  Each of the following constraints specifies an illegal physical site for a
  component of type IPAD:
  Symbol "pci_exp_rxn<1>" (LOC=AB2 [Physical Site Type = OPAD])
  The component type is determined by the types of logic and the properties and
  configuration of the logic it contains. Please double check that the types of
  logic elements and all of their relevant properties and configuration options
  are compatible with the physical site type of the constraint.
..
..
..
..
..
..
ERROR:Pack:1107 - Unable to combine the following symbols into a single OPAD component: BUF symbol "pci_exp_txp_7_OBUF" (Output Signal = pci_exp_txp<7>)
  PAD symbol "pci_exp_txp<7>" (Pad Signal = pci_exp_txp<7>)
  An IO component of type OPAD was chosen because the IO contains symbols
  and/or properties consistent with output usage and also connected directly to
  a Black Box symbol.
  Each of the following constraints specifies an illegal physical site for a
  component of type OPAD:
  Symbol "pci_exp_txp<7>" (LOC=AP3 [Physical Site Type = IPAD])
  The component type is determined by the types of logic and the properties and
  configuration of the logic it contains. Please double check that the types of
  logic elements and all of their relevant properties and configuration options
  are compatible with the physical site type of the constraint.


Mapping completed.
See MAP report file "xilinx_pci_exp_ep_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors : 32
Number of warnings : 12

Process "Map" failed
Text Editor launch cancelled.


Could you please help me how I can resolve these errors !? what I did wrong here?
thanks in advance !



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1 Solution

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Highlighted
Professor
Professor
9,329 Views
Registered: ‎08-14-2007

You've run into the confusing world of PCI express signal directions!

 

PETxxx signals are the transmit signals on the host system (e.g. PC motherboard)

 

PERxxx signals are the receive signals on the host system.

 

The ML555 is not a host, but a plug-in card.  So PETxxx go to the receiver pins of

your design and vice versa.

 

So you should have instead:

 

 NET "pci_exp_rxp<0>" LOC ="W1";
NET "pci_exp_rxn<0>" LOC ="Y1"; 

. . .

 

and

 NET "pci_exp_txp<0>" LOC ="V2";
NET "pci_exp_txn<0>" LOC ="W2";

 

Regards,

Gabor

-- Gabor

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Highlighted
Professor
Professor
9,330 Views
Registered: ‎08-14-2007

You've run into the confusing world of PCI express signal directions!

 

PETxxx signals are the transmit signals on the host system (e.g. PC motherboard)

 

PERxxx signals are the receive signals on the host system.

 

The ML555 is not a host, but a plug-in card.  So PETxxx go to the receiver pins of

your design and vice versa.

 

So you should have instead:

 

 NET "pci_exp_rxp<0>" LOC ="W1";
NET "pci_exp_rxn<0>" LOC ="Y1"; 

. . .

 

and

 NET "pci_exp_txp<0>" LOC ="V2";
NET "pci_exp_txn<0>" LOC ="W2";

 

Regards,

Gabor

-- Gabor

View solution in original post

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Highlighted
Visitor
Visitor
7,999 Views
Registered: ‎11-21-2009
Thank you for your help Gabor !!
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Highlighted
Professor
Professor
7,991 Views
Registered: ‎08-14-2007

I found this out the hard way - a new board design with the transmit and receive

signals swapped to the card edge connector.  Better to find out that your FPGA

pinout is wrong and not the board pinout.

 

Regards,

Gabor

-- Gabor
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Participant
Participant
7,988 Views
Registered: ‎09-18-2009

And it's not necessary to place serial data io pins, but the corresponding GTP-s, as they are locked to the GTPs.

I only have the GT reference clock placed...

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Highlighted
Visitor
Visitor
7,962 Views
Registered: ‎11-21-2009

Tank you again!

now I haven't error in the ucf. 

I would like to transmit data from a counter in card to the pc and I explained it in detaile in a new post as "Writing DATA from PCIe(ml555) Card to a File !!! "

could you please read and send me some comments? maybe this happen because of bad connecting those signals to the fpga pins.

 

regard.

 

 

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