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Contributor
Contributor
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Registered: ‎10-29-2016

UltraScale Devices Gen3 Integrated Block for PCI Express v4.4's example design: Root Port's bus master enable bit cannot be set

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"UltraScale Devices Gen3 Integrated Block for PCI Express v4.4" is used as Endpoint in my design.

 

In the example design of "UltraScale Devices Gen3 Integrated Block for PCI Express v4.4" created by Vivado, 

the following code is used to set the Root Port's command register.

board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h01, 32'h00000007, 4'h1);

The cfg_function_status changed from 0x88 to 0x8b, showing that Root Port's bus master enable bit is still 0(cfg_function_status[2] is bus master enable bit).

bus master enable.PNG

 

I've run the simulation in  Vivado 2018.1 and 2019.2, the results are same.

There are a few threads about bus master enable bit cannot be set, 

but I cannot find the convincing solutions.

 

Is there a bug in the root port of example design?

 

I also configured the IP as the root port, and find that the bus master enable bit of the root port IP cannot be set, either.

Can I think that the bus master enable bit of root port should not be set to 1? 

 

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Xilinx Employee
Xilinx Employee
289 Views
Registered: ‎07-26-2012

The Bus Master Enable bit in the command register can be set, but cfg_func_status [2] does not reflect the value in the command register for RP. This is the same behavior as the 7 series Gen3 core (Page 37 of PG023), but PG213 does not mention it.

Regarding this, I file a change request for the document.

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Xilinx Employee
Xilinx Employee
290 Views
Registered: ‎07-26-2012

The Bus Master Enable bit in the command register can be set, but cfg_func_status [2] does not reflect the value in the command register for RP. This is the same behavior as the 7 series Gen3 core (Page 37 of PG023), but PG213 does not mention it.

Regarding this, I file a change request for the document.

View solution in original post

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Contributor
Contributor
271 Views
Registered: ‎10-29-2016

Thanks for you answer, @kurihara .

 

Do you mean the following picture?

busmasterexception.PNG

The Bus Master Enable bits of EP and RP can be set, but only EP's cfg_function_status[2] will be set.

The only way to confirm wether Root Port's Bus Master Enable is set or not, is to read the Root Port's command register,

and check the Bus Master Enable bit.

 

Is my understanding correct?

 

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Xilinx Employee
Xilinx Employee
259 Views
Registered: ‎07-26-2012

Yes. Your understanding is correct.

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Contributor
Contributor
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Registered: ‎10-29-2016

Thanks very much, @kurihara .

I accepted your answer as the solution.

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