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cfgardiner
Visitor
Visitor
1,095 Views
Registered: ‎09-09-2017

UltraScale+ MPSoC e.g. ZCU102 board: Understanding MSI / MSI-X to PCIe/PS running as root-complex

Hi,

I am trying to set up a root-complex demo for a customer on the ZCU102 board and have some problems understanding how MSI/MSI-X is supposed to work. Target is a barebone application.

 

If I look in the register set https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html, there seem to be two registers for catching  inbound MSI/MSI-X in the ingress, MSGF_MSI_STATUS_LO and MSGF_MSI_STATUS_HIGH. There is mention of two thirty-two bit vectors recording a total of 64 MSI vectors. But this is just nonsense isn't it? PCIe defines only 32 MSI vectors. Also, the vectors to which MSI-X refers are really just address locations, up to 2K per device function. Whereas by MSI the MSI vector is coded in the lower 5 bits of the half-dword payload, MSI-X does to my knowledge not really define what should be in the single DWord payload at all. This is system specific. Vector differentiation is primarily based on the MSI-X target address.

 

Is there any more detailed information describing how MSI/MSI-X events are reported to the a53 cores? Yes, I am aware that there are five interrupts from the GIQ to the core complex, but how does the software then find out the real interrupt source? Does it have to poll each device function which could conceivably cause an interrupt? I don't see where the address and content of an MSI/MSI-X event are temporarily stored and made visible to SW. And again what exactly causes the bits in MSGF_MSI_STATUS_LO/HI to get set? What are the restrictions on MSI/MSI-X in the MPSoC PS? Purely from the PCIe spec, there should be up to 64K x 32 MSI interrupt vectors available in a system and up to 64K x 2K MSI-X vectors. (64K = 256 bus numbers x 32 devices x 8 functions). There can of course be overlap here since no device function is allowed to generate MSI and MSI-X. What exactly are the limitations imposed on MSI/MSI-X in MPSoC/PS (UltraScale+)?

 

Thanks in advance for any guidance.

 

 

 

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deepeshm
Xilinx Employee
Xilinx Employee
994 Views
Registered: ‎08-06-2008

Hi,

MSI-X is not supported in PS-PCIe with RP configuration.

Please refer to the following documents.

https://www.xilinx.com/Attachment/Xilinx_Answer_71210_PS_PL_PCIe_Drivers_Debug_Guide.pdf

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

Please let us know if your queries are still not addressed.

Thanks.

 

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