UltraScale+ PCIe reference clock

[posse]

I'm developing an UltraScale+ MPSoC board that features an M.2 SSD, connected through PCIe x4, and would like to confirm my reference clock design, as reading UG576 still left me in doubt.

As per chapter 2 of UG576, I can provide a 100/125/250MHz reference clock, generated by an oscillator, to one of the differential clock pairs on the GTH transceiver bank (bank 224 in my case). I can then use the other differential clock pair as an output, to forward the reference clock to the M.2 SSD. In this setup, I require only one differential oscillator, and the clock is buffered at the UltraScale device. Is this assessment correct?

Or do I require two differential clock references, both with the same frequency, to feed the UltraScale and the M.2 separately? Is it required that these two clocks are in phase, i.e., coming from the same source, or can they be from different physical oscillator devices?

Thank you in advance

[necare81 · Accepted solution]

No that will not work.  The REFCLK output mode can only source the RX Recovered clock not another REFCLK input.

Functionality of a PCIe link with two different ref clocks depends on both devices having asynchronous capability.  Most M.2 cards probably don't have that.  Standard M.2 cards for use in general computers usually require a 100MHz clock and it to be the oscillator source that feeds the ref clock of the root complex.

You need a 100 MHz oscillator with 2 outputs compliant with the PCIe refclk standard or one oscillator and a clock fanout buffer chip with at least 2 PCIe refclk outputs.   A standard fanout buffer may not work as it probably adds too much jitter.