11-10-2019 07:32 PM - edited 11-10-2019 07:43 PM
On our own hardware board, zu11 is connected to an Intel CPU through PCIe directly at 8 lanes. Intel CPU is root complex and zu11 is endpoint.
PIO demo of IP "Integrated block for PCIe" is used in zu11. When the IP is configured in 4 lane mode, we can find Xilinx endpoint device in Intel CPU by typing "lspci". But no Xilinx endpoint device is found after IP is configured in 8 lane mode.
The configure of IP (8 lane mode) is showd below: (vivado 2018.2)
The hardware design is showd below:
Is there a way I can find out what's happening in the PCIe IP block? (Like error status)
11-14-2019 11:44 PM
11-19-2019 10:20 PM
This is the GT port name. When inserting ILA, if you check the port connection of GT components in the netlist, you can select the appropriate net.