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Participant
Participant
411 Views
Registered: ‎02-14-2019

UltraScale+ PL endpoint PCIe: 4 lane can work but 8 lane can't

On our own hardware board, zu11 is connected to an Intel CPU through PCIe directly at 8 lanes. Intel CPU is root complex and zu11 is endpoint.

PIO demo of IP "Integrated block for PCIe" is used in zu11. When the IP is configured in 4 lane mode, we can find Xilinx endpoint device in Intel CPU by typing "lspci". But no Xilinx endpoint device is found after IP is configured in 8 lane mode.

The configure of IP (8 lane mode) is showd below: (vivado 2018.2)Selection_050.png

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The hardware design is showd below:

Selection_051.png

Is there a way I can find out what's happening in the PCIe IP block? (Like error status)

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Xilinx Employee
Xilinx Employee
337 Views
Registered: ‎07-26-2012

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Participant
Participant
299 Views
Registered: ‎02-14-2019

How can I check the status like "TXDETECTRX" in PL. I am confused becasue there is no PIN called this name. Is it a register in PCIe IP? 

Thanks.

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Xilinx Employee
Xilinx Employee
269 Views
Registered: ‎07-26-2012

This is the GT port name. When inserting ILA, if you check the port connection of GT components in the netlist, you can select the appropriate net.