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Visitor
Visitor
402 Views
Registered: ‎09-06-2019

Ultrascale PS PCIe endpoint not responding

Vivado 2018.3

UltraZed-EG on PCIe carrier card

 

Hello,

I am implementing the PS PCIe endpoint by following the example found in Answer 72076.  I am using the source files found in that example (pcie_ep_pio.h and .c). Why do I not see the endpoint device interrupts when I write to the DMA0 scratchpad at BAR0, the LEDs at BAR1 or DDR at BAR2?

After creating a boot file with a FSBL, .bit file and the PCIe application example I am able to load it onto the QSPI flash.  I then install it on a Windows 7 PC and boot the computer.

To test the PCIe response, I am using a utility called PCIScope.  This utility discovers the Xilinx device and enumerates BAR0, BAR1 and BAR2 as I have configured it.  I can also write to the command register in configuration space to allow writes to memory (bit 1 of the command register). 

I then try to write to BAR0, which should be translated to the bridge inside the endpoint device.  In my system BAR0 is at 0xFDC00000.  I execute a write to 0xFDC00050 which should hit the address for the DMA scratchpad 0 register, but I do not get a response to the serial port output from the interrupt service routine to indicate the write was received by the endpoint.

I also see a Master Transaction Abort when I try to read from Memory Space.

The example application uses a serial port output to demonstrate the endpoint is running and report register translations. The main loop is shown below. 

 

int main(void)

{

       u32 val;

       u32 bar_base_lo, bar_base_hi;

 

       printf("PCIE Ingress Test start \n");

       InitIntr();

       printf("Interrupt initialized\n");

       printf("Waiting for PCIe Link up\n");

       do {

              val = Xil_In32(PCIE_STATUS);

       } while (!(val & PCIE_LINK_UP));

       printf("PCIe Link up...\n");

       BridgeInit();

       printf("Bridge Init done...\n");

       /*

       * Wait for the host to enumerate us.

       * on x86 BIOS sets memory enable bit

       * on ARM64 it is set when driver gets inserted

       */

       do {

                     val = Xil_In32(COMMAND_REG);

                     usleep(10);

       } while (!(val & 0x00000002U));

       printf("Host driver indicated ready\n");

       //read_bar_JRL(BAR_NUM2, &bar_base_lo, &bar_base_hi, BAR2_SIZE);

       read_bar(BAR_NUM2, &bar_base_lo, &bar_base_hi);

       SetupIngress(bar_base_lo, bar_base_hi, PS_DDR_ADDR, INGRESS_SIZE_ENCODING, INGRESS_NUM0);

       printf("Set up BAR2 to DDR (I hope!)\n");

       //read_bar_JRL(BAR_NUM1, &bar_base_lo, &bar_base_hi, BAR1_SIZE);

       read_bar(BAR_NUM1, &bar_base_lo, &bar_base_hi);

       SetupIngress(bar_base_lo, bar_base_hi, MY_LEDS, INGRESS_SIZE_ENCODING, INGRESS_NUM1);

       printf("Set translation to LEDs (I hope!)\n");

       printf("DDR:   ");

       DisplayIngress(INGRESS_NUM0);

       printf("LEDs:   ");

       DisplayIngress(INGRESS_NUM1);

       printf("running1");               /////////////////  This line never prints to the console

       count=0;

       while (1)

       {      if (count<=1)

              {

                     printf("running2");  ///////////    This line never prints to the console

              }

              count++;

       };

       printf("PCIE Ingress Test done\n");

       return 0;

}

I have added a few printf statements  just before the while(1) loop to help debug.  The program runs to the second “DisplayIngress(INGRESS_NUM1)” function call and executes printf() status statements within that function.  I do not see the next line of the program executed, which is “printf(“running1”); and I do not see the printf() statement within the while(1) loop.

What is even stranger is I have run this in debug mode and the program does get into the while(1) loop, but the final printf() statements are not being output.

This is the serial port output I get when running.

Interrupt initialized

Waiting for PCIe Link up

PCIe Link up...

Bridge Init done...   **********The output waits here until I write to the command register in configuration space to allow memory writes*****************************

Host driver indicated ready
BAR Read
BAR2 LO configured by host 0x4157669376x
BAR2 HI configured by host 0x0x
Done writing the Ingress Src registers
Done writing the Ingress Dst registers
Read Ingress Control register
Set ingress control register to ff800005, 4286578693
Done setting up the ingress trasnslation registers
Set up BAR2 to DDR (I hope!)
BAR Read
BAR1 LO configured by host 0x4157603840x
BAR1 HI configured by host 0x0x
Done writing the Ingress Src registers
Done writing the Ingress Dst registers
Read Ingress Control register
Set ingress control register to ff800005, 4286578693
Done setting up the ingress trasnslation registers
Set translation to LEDs (I hope!)
DDR: Displaying translation for Region 0
fd0e0810 : f7d10000
fd0e0814 : 0
fd0e0818 : 80001000
fd0e081c : 0
fd0e0808 : ff800005
done Ingress report
LEDs: Displaying translation for Region 1
fd0e0830 : f7d00000
fd0e0834 : 0
fd0e0838 : 80000000
fd0e083c : 0
fd0e0828 : ff800005
done Ingress report

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1 Reply
Highlighted
Newbie
Newbie
189 Views
Registered: ‎03-27-2020

Re: Ultrascale PS PCIe endpoint not responding

Could you have any progress about your Pcie question?

i also had some questions at test Ultrascale PS PCIe endpoint, the Pcie  link-up failed; 

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