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brent.aandd
Observer
Observer
448 Views
Registered: ‎02-15-2018

Ultrascale Tandem configuration with asynchronous clock

Hello,

I am using a Tandem configuration so PCIe boots in time for PCIe enumeration. I would like to use a Asynchronous PCIe reference clock. When testing with asynchronous clock, I noticed that Tandem was not booting in time for enumeration. In this case the PCIe bus never gets past the polling states. If I then soft reboot system (no FPGA configuration), the  PCIe will properly enumerate.

If I switch to a synchronous "slot clock", the PCIe will boot without problem or need to soft boot.

Any Ideas what may be causing problem?

Thanks!

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2 Replies
deepeshm
Xilinx Employee
Xilinx Employee
421 Views
Registered: ‎08-06-2008

One immediate thing to check will be to try be disabling SSC.

Thanks

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brent.aandd
Observer
Observer
410 Views
Registered: ‎02-15-2018

Thanks for the response. I assume you are talking about the on-board clock configuration and not an IP setting. If yes, I already checked the clock and it does not have SSC output.

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