I am working on a design using AXI Mapped Memory to PCI Express IP. So far the design used two clock inputs from different sources: 1.) pcie_clk (100 Mhz) from MGTREFCLK0 pins as REFCLK for the AXI Mapped Memory IP 2.) sys_clk (100 Mhz) from two MRCC pins to generate a system clock of 200 Mhz.
From my understanding it is better to avoid asynchronous clocks.
Is there a proper way to generate the system clock avoiding the second clock input? So far i have tried connecting a Clock Wizard to the IBUFDS_GTE2 .O output and selected "No buffer" as Source for the Clock Wizard Input Clock. This works, however i am curious whether there is a better solution.
This shows the current solution with Clock Wizard being connected to IBUFDS_GTE2 .O output. Target is an xc7k70t