03-04-2011 06:21 AM
I'm verifing the my design based on PCIe_v1_14 Xilinx IP.
My design logic transmits dsport the memory write TLP.
Because I don't know the dsport address, I don't verify that transmitted TLP is or isn't received by the dsport.
What I do?
If the dsport's BAR is, do you know it?
03-05-2011 05:31 PM