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pclet
Visitor
Visitor
4,651 Views
Registered: ‎01-27-2011

User design PCIe device transmits the memory write TLP.

Hi,

 

I'm verifing the my design based on PCIe_v1_14 Xilinx IP.

My design logic transmits dsport the memory write TLP.

Because I don't know the dsport address, I don't verify that transmitted TLP is or isn't received by the dsport.

What I do?

If the dsport's BAR is, do you know it?

 

Regards

Michael

 

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3 Replies
luisb
Xilinx Employee
Xilinx Employee
4,624 Views
Registered: ‎04-06-2010

The root port should accept all packets that come in. The only requirement is that the TLP is not malformed. You also need to make sure that the endpoint's Bus Master Enable bit is set so that it's allowed to send a packet upstream.
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pclet
Visitor
Visitor
4,616 Views
Registered: ‎01-27-2011

Hi Luisb,

 

Where is the endpoint's Bus Master Enable bit?

 

Regards

Michael

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luisb
Xilinx Employee
Xilinx Employee
4,599 Views
Registered: ‎04-06-2010

This is bit 2 of the command register in the endpoint's type 0 config space.

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