07-29-2019 07:44 PM
Is there any way to use 3rd party PCIe VIP to do DMA access through Xilinx XDMA design? I am reading the xilinx-xdma document, but I didn't find any clue about it.
08-06-2019 08:41 AM
Hi @mushihao ,
Generate the IP example design and do simulation. You can know how to initiate DMA transfer from the Root port model.
08-06-2019 01:06 PM
Hi @venkata ,
Thanks. I already checked the example design and I think it sent transactions through AXI stream interface then to the root port model. I would like to know what is the data packet (addr and data pair) in pcie root port model directly. Please let me know if I misunderstood anything.
08-06-2019 03:19 PM
If you are looking to check the packet received at the root port, you will have to refer to the documentation of the VIP to know the signals to check.
IP example design helps to understand how does the test bench setup the descriptor and initiates the transfer from endpoint to the root port. If you refer the test bench model, you can find the details.