We are thinking of using the Avnet PicoZed AES-Z7PZ-7Z030-SOM-G for prototyping the Synopsys PCIe EP IP. Following are my questions
1. Can I used the 4 GTX transceivers independent of the PCIe Integrated IP and instead integrate the Synopsys PCIe IP to it?
2. Does Xilinx have any PHY IP that gives out a PCIe PIPE interface which can be used to integrate the Synopsys PCIe IP
You should talk to Avnet, and Synopsys.