10-21-2011 06:59 AM
I have a small AXI memory mapped design that contains 1 axi_pcie, 1 axi_v6_ddrx and 1 axi_cdma.
The axi_cdma is connected as master on both axi_v6_ddrx slave and axi_pcie slave.
The axi_pcie is also connected as master on an AXI-lite interconnect (to access axi_cdma slave registers).
This way, I want the Host CPU to program the axi_cdma so that it can transfer data between the AXI DDR (on the FPGA side) and the PCIe DDR (on the Host side).
The problem is that I don't understand how to configure the axi_cdma ; the only addresses it knows are AXI addresses, not PCIe addresses. How is the translation performed?
If I configure the axi_cdma with AXI addresses, how will those AXI addresses be translated into PCIe addresses?
Thank you for your help.
10-22-2011 08:00 AM
You're going to need to map a BAR to the CDMA core so that the host can write to the DMA. This is done by setting the C_PCIEBAR2AXIBAR_# to the CDMA base address. I recommend reading over Example 3 in the Data Sheet under the Address Translation section. This is on page 24 and 25.
If you read this section and this doesn't make sense, let me know.
11-08-2011 08:38 AM
Thanks for your answer.
I understand how to access the PCIe BAR from the Host CPU.
My question was more about the addresses I have to write to configure the DMA.
Imagine I have a 8-KiB virtual buffer on the Host memory, composed of two 4-KiB physically continuous pages (@ PCIe address 0x12345678 and PCIe address 0x23456789 for example, please forget about the nasty alignments).
I want to start a 8-KiB DMA from the AXI address 0x00000000 (up to AXI address 0x00001fff) to this Host virtual buffer (bus mastering).
How do I configure the scatter-gather DMA (because it does not know the PCIe addresses and only knows about AXI addresses)?
11-10-2011 02:01 AM
I think in BRAM would be the best option (no latency for fetching descriptors) as I can limit the size of a DMA to 1 MiB (hence 256 pages of 4KiB which leads to 256 descriptors).
11-27-2011 07:29 AM
The descriptors are going to need to contain AXI address because that's what the CDMA uses for SA or DA.
When you're setting up these addresses, you need to ensure that it's going to translate correctly by making sure the AXIBAR2PCIEBAR_## are set up correctly. The AXIBAR2PCIEBAR_## register can be written to via the Control Interface. These registers are read/write registers, so you can check them and update them on the fly.
Hope this helps.
02-07-2012 03:04 PM
I have to do a simular task as araquirit.
What do you especially mean with "so you can check them and update them on the fly."
As I know you cannot write from an 64-bit AXI to an 32-bit AXI-Lite-Bus, don't you? So you are not able to modify the AXIBAR2PCIEBAR_## register on the fly, are you?
Thanks for your response!
02-15-2012 06:03 PM