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jacob.guttman
Contributor
Contributor
9,748 Views
Registered: ‎12-16-2009

V5 PCIe Expansion ROM not reponding

I am working on a V5 PCIe system which, by default has the Expansion ROM set. I inharited the system and all else works fine. I am trying to simulate an access to this ROM by setting BAR6 (offset 0x30) to 0x55500001 and then writing to memory address

0x555000000 some data. It does not respond. Can someone clarify a few things for me:

- Should I use 32bit or 64bit access?

- Since it is a default Xilinx setting what else can I do ?

- The core does not generate the trn_rbar_hit_n[6]

 

Thanks,

J.G.

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kotir
Scholar
Scholar
9,735 Views
Registered: ‎02-03-2010

Hi ,

 

This is a 1MB 32 bit BAR for EROM in blk plus core.

There will be rbar_hit_n [6] signal asserted on teh trn_* interface

Can you try the cfg read of the base address of this BAR to match with the packet sent by the RP ?

Does the root port receive the completin with UR status for any mem rd for the EROM bar?

 

Regards,

KR

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jacob.guttman
Contributor
Contributor
9,722 Views
Registered: ‎12-16-2009

I am using a BFM from a company called PLDA so I was using a 64bit write/read command on this XROM which is a 32bit BAR. However, now that I'm using a 32bit  DWORD write command it responds (I get a trm_hit[6]) ok but when I try to read I get the error:

 

XILINX_PCIE_308 : USER INTERFACE PACKET WRITTEN WITH INCORRECT AMOUNT OF DATA
# ERROR at 44326 ns :  : packet ended with a EDB

 

Any ideas?

 

Thanks,

JG

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liy
Xilinx Employee
Xilinx Employee
9,713 Views
Registered: ‎08-02-2007

can you re-check the commend ,  it is really read not write?

 

is it possible there is one bit error in the command ?

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jacob.guttman
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9,699 Views
Registered: ‎12-16-2009

Yeah, the format of the command was supposed to be 4'1111 and I had it as 3'111, in fact I was writing one less byte...

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