01-26-2015 11:40 AM
I am working on a V5 PCIe system which, by default has the Expansion ROM set. I inharited the system and all else works fine. I am trying to simulate an access to this ROM by setting BAR6 (offset 0x30) to 0x55500001 and then writing to memory address
0x555000000 some data. It does not respond. Can someone clarify a few things for me:
- Should I use 32bit or 64bit access?
- Since it is a default Xilinx setting what else can I do ?
- The core does not generate the trn_rbar_hit_n
01-27-2015 04:01 AM - edited 01-27-2015 04:02 AM
This is a 1MB 32 bit BAR for EROM in blk plus core.
There will be rbar_hit_n  signal asserted on teh trn_* interface
Can you try the cfg read of the base address of this BAR to match with the packet sent by the RP ?
Does the root port receive the completin with UR status for any mem rd for the EROM bar?
01-27-2015 02:30 PM
I am using a BFM from a company called PLDA so I was using a 64bit write/read command on this XROM which is a 32bit BAR. However, now that I'm using a 32bit DWORD write command it responds (I get a trm_hit) ok but when I try to read I get the error:
XILINX_PCIE_308 : USER INTERFACE PACKET WRITTEN WITH INCORRECT AMOUNT OF DATA
# ERROR at 44326 ns : : packet ended with a EDB
01-27-2015 06:53 PM
can you re-check the commend , it is really read not write?
is it possible there is one bit error in the command ?