cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
3,646 Views
Registered: ‎03-10-2008

V6 PCIe Endpoint Example Design Testbench

I have generated a PCIe endpoint example design testbench in VHDL.  I am surprised at the sixty-odd files necessary to put this together!  Nevertheless, it runs the simple configuration read example provided called the sample_smoke_test0 test.  I have also built the equivalent in Verilog but find that the test approach is different and I have idependent tools for VHDL simulation.  I have reviewed the commands and code in test_interface.vhd and listed in the attachment.  Does anyone have an example that shows how to properly use these Root Complex commands to configure a BAR and access the endpoint application space?

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
3,599 Views
Registered: ‎08-06-2008

Re: V6 PCIe Endpoint Example Design Testbench

If you generate V5 block plus core in verilog it comes with an example test where you could read from the endpoint backend memory space. The name of the test is called  pio_writeReadBack_test0. The generated project will have three files in simulation/tests directory:

 

sample_test1.v

tests.v

pio_tests.v

 

You could copy these three files into the project for V6 PCIe example design. You will then need to change the simulate_mti.do file to use the new test pio_writeReadBack_test0 instead of sample_smoke_test0.

 

0 Kudos