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Visitor
Visitor
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Registered: ‎10-24-2018

VC707 PCIe clock not available in block design

I have been trying to get PCIe DMA block to read/write to DDR3 memory on VC707 board that has a Virtex-7 FPGA.

I'm following instructions from: https://www.xilinx.com/video/technology/dma-for-pci-express.html

However, I do not get "pci_refclk" in my Block Design on Vivado. The block/connection automation steps do not produce it on the page. And I can figure out no method to place it manually. I only have "sys_diff_clock" which is the 200MHz onboard clock signal.

I see from VC707 manual that PCIe differential clock is input from the edge connector and routed to FPGA pins AB8 (P) and AB7 (N). My understanding (from the video above) is that I need to connect it to my PCIe-DMA block through a utility buffer (which makes it single ended).

So, how do I get this resolved? Am I right in my understanding that the PCIe clock signal from the edge connector needs to be routed to the PCIe-DMA block? Or would another 100MHz clock (derived from sys_clock) suffice?

PS: In the attached diagram, I have the sys_clk input of the PCIe-DMA block routed to a 100MHz clock generated by the DDR3 MIG block.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Capture.JPG

In general, the input clock should meet the PCIe spec requirement.

Thanks.

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Visitor
Visitor
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Registered: ‎10-24-2018

Specifically, can we connect any suitable clock signal to it or it has to be the clock input from the edge connector?

I managed to connect it by defining a new signal and then mapping it to the edge connector pins using the constraints file. It had to be routed through an IBUF_GTE type utility buffer block (typing from memory).

Now the device shows up on lspci output on host PC. Couldn't test actual data transfer as the DMA driver module keeps crashing on startup.

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