01-27-2011 02:32 PM
I am attempting to create a specman 'e' testbench to verify a VHDL Xilinx design that has a Spartan-6 PCIe endpoint core.
I do not want to develop a PCIe interface to drive the DUT however I find the example testbench difficult to connect
to my 'e' testbench. So what I tink I want to do is to use the pcie_2_0_rport_v6 entity that is the testbench and drive
that from the testbench directly.
My problem is I am not a PCIe expert so I am not sure how the initialization and configuration of the cores (simulation) works. Can you suggest any documents that will help? I am familuar with the interface for endpoint core, but not for the root core. Again can you point me to any documentation on how to use the pcie_2_0_rport_v6 entity?
01-27-2011 07:47 PM
I would recommend using the root port model that is generated when you generate the core. There are two primary files that you can modify to generate your own tests. The two files are located in the following directory:
If you look in the tests.vhd file you'll see that there's a procedure called PROC_SYSTEM_INITIALIZATION. This procedure is defined in the test_interfaces.vhd. In the test_interfaces.vhd you can see exactly what the root port does to enumerate the device. You should see the configuration reads and writes. You can modify them if you'd like.
Hopefully this will help you get started...
01-31-2011 01:37 AM