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bemiller
Visitor
Visitor
6,076 Views
Registered: ‎01-27-2011

Verifying a PCIe endpoint design

Hello There,

I am attempting to create a specman 'e' testbench to verify a VHDL Xilinx design that has a Spartan-6 PCIe endpoint core.
I do not want to develop a PCIe interface to drive the DUT however I find the example testbench difficult to connect
to my 'e' testbench. So what I tink I want to do is to use the pcie_2_0_rport_v6 entity that is the testbench and drive
that from the testbench directly.

My problem is I am not a PCIe expert so I am not sure how the initialization and configuration of the cores (simulation) works. Can you suggest any documents that will help? I am familuar with the interface for endpoint core, but not for the root core. Again can you point me to any documentation on how to use the pcie_2_0_rport_v6 entity?

Thanks
Brian Miller
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4 Replies
luisb
Xilinx Employee
Xilinx Employee
6,069 Views
Registered: ‎04-06-2010

I would recommend using the root port model that is generated when you generate the core.  There are two primary files that you can modify to generate your own tests.  The two files are located in the following directory:

 

<core name>/simulation/dsport/test_interfaces.vhd

<core name>/simulation/tests/tests.vhd

 

If you look in the tests.vhd file you'll see that there's a procedure called PROC_SYSTEM_INITIALIZATION.  This procedure is defined in the test_interfaces.vhd.  In the test_interfaces.vhd you can see exactly what the root port does to enumerate the device.  You should see the configuration reads and writes.  You can modify them if you'd like.

 

Hopefully this will help you get started...

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bemiller
Visitor
Visitor
6,048 Views
Registered: ‎01-27-2011

Is ther any doc that can explain what the procedure PROC_BAR_INIT is doing. I think this is the main point that I don't understand.

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luisb
Xilinx Employee
Xilinx Employee
6,020 Views
Registered: ‎04-06-2010

There isn't a doc that explains all of the procedures, however, you should be able to read them in the HDL.  They are pretty straight-forward.  

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deepeshm
Xilinx Employee
Xilinx Employee
5,976 Views
Registered: ‎08-06-2008

Hi,

 

Please find a document attached. This is an internal and unofficial document. There might be plenty of typos. :o)

However it might be helpful.

 

Thanks.

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