04-02-2021 01:54 AM - edited 04-02-2021 01:57 AM
Versal architecture feature a mix of next-generation Scalar Engines, Adaptable Engines, and Intelligent Engines. High performance connectivity is fundamental to compute acceleration and PCI Express is one of the data highways that addresses a wide range of functional and performance needs for the multiple compute engines in Versal ACAPs. New CPM block available in Versal ACAPs, which features Gen4 x 16 capability.
Read more about Versal in https://www.xilinx.com/support/documentation/white_papers/wp505-versal-acap.pdf .
PCIe board guidelines
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Versal PCIe Solution
This post will cover all necessary information you should know before starting to build PCIe based designs on Versal ACAP devices.
There are two basic design flows to use when targeting Versal ACAP
Vivado IP Integrator is the primary flow for non-AI Engine-based projects and is recommended to use for designs creation targeting Versal.
Please refer to Chapter 3 - “Design Creation with IP Integrator” in Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387), and Chapter 4 – “Design Flow” in Versal ACAP Design Guide (UG1273)
Most of the PL IPs are documented separately pointing to Versal TRM. Use Block Automation within IP Integrator for PL PCIe IP to GT integration. Please refer to PG331 Chapter 4 - “Xilinx IP - GT Quad Integration” for more details.
CIPS IP, which contains the PMC used to boot the device. For more information, see the Control Interface and Processing System IP Product Guide (PG352).
Versal PCIe cores
With Versal devices, PCIe solutions are available as part of processing subsystem (CPM) and as PL PCIe IPs.
|PCIe IP core||Features||Example Design|
IP Product Guides and Master ARs
Here is a list of the PCIe IPs with their product guides, release notes and known issues master ARs consolidated in https://www.xilinx.com/support/answers/34536.html.
|IPs||Product/User Guides||Master ARs|
Versal ACAP TRM
|Versal ACAP Reference Register||AM012|
|Versal Product Datasheet||DS950|
|Versal ACAP Integrated Block for PCI Express||PG343||https://www.xilinx.com/support/answers/73083.html|
|Versal ACAP PHY for PCI Express||PG345||https://www.xilinx.com/support/answers/72289.html|
|Versal ACAP CPM Mode for PCI Express||https://www.xilinx.com/support/answers/75350.html|
Versal ACAP CPM DMA and Bridge Mode for PCI Express
|Versal ACAP DMA and Bridge Subsystem for PCI Express||PG344 (to be released soon)||https://www.xilinx.com/support/answers/75397.html|
|Versal ACAP QDMA||PG to be released|
|Versal AXAP CPM CCIX||AM016|
Versal PCIe Drivers
The wiki pages document the support features and known issues, and drivers can be found on github. Refer to wiki page for Versal CPM & PL PCIe driver information.
Versal PCIe Debug
Added PCIe EoU Debug Cockpit for Versal Integrated PCI Express block i.e. PCIe IP configuration has option to enable PCIe link debug interface module which will automatically add in ILA/VIO debug IPs.
Versal™ architecture has an Integrated Block for PCI Express® with DMA and Cache Coherent Interconnect (CPM) block and it also continues to offer a PL PCIE much improved from that available in previous architectures.
Place request for the Versal Premium documents from the lounge to get access.
04-02-2021 02:26 AM
Great content for Versal CPM and PCIe. I look forward to seeing more additions to the content as the Versal devices and, CPM and PCIe IPs mature.