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pvenugo
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Registered: ‎07-31-2012

Versal CPM & PCIe - Resources

 

Versal

Versal architecture feature a mix of next-generation Scalar Engines, Adaptable Engines, and Intelligent Engines. High performance connectivity is fundamental to compute acceleration and PCI Express is one of the data highways that addresses a wide range of functional and performance needs for the multiple compute engines in Versal ACAPs. New CPM block available in Versal ACAPs, which features Gen4 x 16 capability.

Read more about Versal in https://www.xilinx.com/support/documentation/white_papers/wp505-versal-acap.pdf .

 

PCIe board guidelines

 

Note: When initiating a forum post, please don’t forget to mention the following details at the start: 

  • Vivado Version (e.g. 2020.2, 2020.1 etc.)
  • Name of the IP (e.g. CPM - PCIe, DMA and CCIX, XDMA, AXI Bridge, QDMA etc. )
  • Device Family (e.g. Versal AI Core, Versal Prime etc.)

If the below information does not help, please post it in the forum with the details of the investigation you have done, screenshots of ILA waveforms (if applicable), screenshots of error messages, screenshot of document if you are referring to a specific section or paragraph, block diagram of your design (if can be shared),system details such as which host system is being used etc. The detailed information will be extremely helpful for the community, for us to try and provide you useful information to debug your issue.

Note: If you have any debugging techniques/tips, please feel free to create a new post with the details of your experience using the PCIe IP. This will be helpful for the community and will also be a very good feedback for us to improve our product and documentation. We would really appreciate your help.

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Versal PCIe Solution

This post will cover all necessary information you should know before starting to build PCIe based designs on Versal ACAP devices.  

 

Design Flow 

There are two basic design flows to use when targeting Versal ACAP

  1. Vivado Tools Design Flow
  2. Vitis Environment Design Flow

Vivado IP Integrator is the primary flow for non-AI Engine-based projects and is recommended to use for designs creation targeting Versal.  

Please refer to Chapter 3 - “Design Creation with IP Integrator” in Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387), and Chapter 4 – “Design Flow”  in Versal ACAP Design Guide (UG1273)

Most of the PL IPs are documented separately pointing to Versal TRM. Use Block Automation within IP Integrator for PL PCIe IP to GT integration. Please refer to PG331 Chapter 4 - “Xilinx IP - GT Quad Integration” for more details.  

CIPS IP, which contains the PMC used to boot the device. For more information, see the Control Interface and Processing System IP Product Guide (PG352). 

 

Versal PCIe cores

With Versal devices, PCIe solutions are available as part of processing subsystem (CPM) and as PL PCIe IPs.  

PCIe IP core Features Example Design
CPM
  1. Integrated block for PCI Express Rev. 4.0 with DMA and CCIX Rev. 1.0 
  2. Use CIPS IP to configure the CPM block in different PCIe modes. 
  3. CPM block contains two controllers. 
  4. Supported use modes with CPM0 – PCIe, DMA and CCIX
    • PCIe and CCIX use modes support End point, Root port, Switch Upstream port and Downstream port types. 
    • DMA use mode can be used to configure CPM0 in XDMA/AXI-Bridge/QDMA modes. 
    • Root Port use mode is only available with "AXI-Bridge" functional mode. 
  5. Supported use modes with CPM0 - PCIe 
    • Can be configured as endpoint and root port use modes. 
 

PL-PCIe IP

  1. Queue DMA Subsystem for PCI Express -- QDMA 
    • Supports QDMA and AXI-Bridge functional modes. 
    • To generate Root Port Bridge IP, use QDMA IP. This is different with Versal when compared to UltraScale+ 
  2. Versal ACAP XDMA Subsystem for PCI Express - pcie_dma_versal 
  3. Versal ACAP Integrated Block for PCI express - pcie_versal 
    • Supports only XDMA mode.  
    • There is no AXI-Bridge function mode but IP has option to enable both slave bridge and master bridge.  

 

IP Product Guides and Master ARs 

Here is a list of the PCIe IPs with their product guides, release notes and known issues master ARs consolidated in https://www.xilinx.com/support/answers/34536.html.

IPs  Product/User Guides   Master ARs 

Versal ACAP TRM

AM011  
Versal ACAP Reference Register AM012  
Versal Product Datasheet  DS950   
Versal ACAP Integrated Block for PCI Express PG343 https://www.xilinx.com/support/answers/73083.html
Versal ACAP PHY for PCI Express  PG345 https://www.xilinx.com/support/answers/72289.html
Versal ACAP CPM Mode for PCI Express

PG346 

https://www.xilinx.com/support/answers/75350.html

Versal ACAP CPM DMA and Bridge Mode for PCI Express

PG347 

https://www.xilinx.com/support/answers/75396.html

Versal ACAP DMA and Bridge Subsystem for PCI Express  PG344 (to be released soon) https://www.xilinx.com/support/answers/75397.html
Versal ACAP QDMA  PG to be released  
Versal AXAP CPM CCIX AM016  

 

Versal PCIe Drivers 

The wiki pages document the support features and known issues, and drivers can be found on github.  Refer to wiki page for Versal CPM & PL PCIe driver information.

 

Versal PCIe Debug

Added PCIe EoU Debug Cockpit for Versal Integrated PCI Express block i.e. PCIe IP configuration has option to enable PCIe link debug interface module which will automatically add in ILA/VIO debug IPs.

 

Blog

Versal™ architecture has an Integrated Block for PCI Express® with DMA and Cache Coherent Interconnect (CPM) block and it also continues to offer a PL PCIE much improved from that available in previous architectures.

 

Lounge

Place request for the Versal Premium documents from the lounge to get access.

 


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1 Reply
garethc
Moderator
Moderator
339 Views
Registered: ‎06-29-2011

Great content for Versal CPM and PCIe. I look forward to seeing more additions to the content as the Versal devices and, CPM and PCIe IPs mature.

Thanks,

Gareth


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