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Visitor
Visitor
6,058 Views
Registered: ‎04-25-2010

Virtex-6 PCIE End Point 1.4 and ISE 11.5, are they good??

xtp045_gen2_creation.pdf was based on Virtex-6 PCIE End Point 1.3 and ISE 11.4. What was the reason it was not using PCIE 1.4, which already existed in ISE 11.4? Unfortunately I started my design using Virtex-6 PCIE End Point 1.4 and ISE 11.5. I figured the latest should be better and didn't pay much attention. I have been modifying the testbench and sample design to fit my need. I have not tested on the board and I'm getting scared now after fixing several issues. Now I'm hit with a bizarre problem and it seems like it's coming from the core. I changed the hierarchy where the core is located and it just did not generate trn_clk any more after reset. I logged all the inputs (asynchronously) to the core and diff against a previous good run. All input events were identical. One run generated trn_clk, the other did not. How could that be!!? Can some confirm that the Virtex-6 PCIE End Point 1.4 and ISE 11.5 together are good, at least in h/w? Should I switch back to 1.3 & 11.4? This would cost me a few days.
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Xilinx Employee
Xilinx Employee
6,044 Views
Registered: ‎08-07-2007

Hi,

 

That doc, xtp025, is for using the ML605 card with the Virtex-6 PCIe block. Currently the ML605 cards have ES (engineering sample) silicon on them. The only version of the core that supports ES silicon is v1.3.

 

So if you have a board with ES silicon, then you should use v1.3 for reliable operation. The v1.4 core may work, but it could have issues.

 

http://www.xilinx.com/support/answers/33276.htm

 

http://www.xilinx.com/support/answers/34009.htm

 

The software version you use should not matter. You can use ISE 11.5 and the v1.3 core if you want to. You will need to download an update found in AR  34739 to work around an issue you will have in map with the MMCM VC0 settings. This udpate can be found here: ftp://ftp.xilinx.com/pub/applications/pci/ar34279_v6_pcie_v1_3.zip

 

http://www.xilinx.com/support/answers/34739.htm

 

Regards

John

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Visitor
Visitor
5,960 Views
Registered: ‎04-25-2010

Hi John, I downgraded my design to 1.3 and ISE 11.4. Anyway it didn't fix my simulation problem. I found that the pcie endpoint only wants to be placed at the top level, the same way that the PIO or BMD example use. When I push it down one more level, it stops working. trn_clk doesn't come out from the core. Can you verify whether this is a simulation model bug or an actual requirement? Thanks, Paul
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Xilinx Employee
Xilinx Employee
5,945 Views
Registered: ‎08-07-2007

HI,

 

You should be able to put the core at any level as long as you adjust the UCF constraints and so forth to match. That is not a restriction. I figure you just have a misconnect somewhere that you are overlooking.

 

If trn_clk is not running - you are saying its flatfline - then I would look down into the wrapper into the pcie_clocking.v module and follow the clocks from there and see what is happening. The trn_clk will originate out of that module. I would try to take it step by step and trace the clock coming in on sys_clk and ensure you have a connection all the way through the design.

 

 

-John

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Visitor
Visitor
5,932 Views
Registered: ‎04-25-2010

I see. I misunderstood that trn_clk was originating from the encrypted core. I see now it's from the clocking module. Unfortunately, I didn't save that design. I'll go back and double-check it when I have more time. One more question: why is rst_n used as synchronous reset in the PIO and BMD examples? Why not async reset as typically done for RTL design? Thanks, Paul
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Xilinx Employee
Xilinx Employee
5,905 Views
Registered: ‎09-02-2009

There has been some bench mark testing done that shows that designs tend to be smaller and more easily meet timing if synchronous resets are used.  Most new designs that target an FPGA use synchronous reset for these reasons.

 

Jason

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