05-04-2010 11:21 PM
05-05-2010 07:21 AM
That doc, xtp025, is for using the ML605 card with the Virtex-6 PCIe block. Currently the ML605 cards have ES (engineering sample) silicon on them. The only version of the core that supports ES silicon is v1.3.
So if you have a board with ES silicon, then you should use v1.3 for reliable operation. The v1.4 core may work, but it could have issues.
The software version you use should not matter. You can use ISE 11.5 and the v1.3 core if you want to. You will need to download an update found in AR 34739 to work around an issue you will have in map with the MMCM VC0 settings. This udpate can be found here: ftp://ftp.xilinx.com/pub/applications/pci/ar34279_v6_pcie_v1_3.zip
05-10-2010 03:58 PM
05-11-2010 07:42 AM
You should be able to put the core at any level as long as you adjust the UCF constraints and so forth to match. That is not a restriction. I figure you just have a misconnect somewhere that you are overlooking.
If trn_clk is not running - you are saying its flatfline - then I would look down into the wrapper into the pcie_clocking.v module and follow the clocks from there and see what is happening. The trn_clk will originate out of that module. I would try to take it step by step and trace the clock coming in on sys_clk and ensure you have a connection all the way through the design.
05-11-2010 07:37 PM
05-12-2010 09:29 PM
There has been some bench mark testing done that shows that designs tend to be smaller and more easily meet timing if synchronous resets are used. Most new designs that target an FPGA use synchronous reset for these reasons.