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patocarr
Teacher
Teacher
6,389 Views
Registered: ‎01-28-2008

Virtex-6 PCIE links at X8, doesn't a X4 or X1.

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Hi folks,

 

  I have a peculiar issue with this custom board, that enumerates without issue at X8 (gen1), but doesn't at X4 or X1. The X8 design uses a non-standard GTX placement, exactly reversed from the generated example design, ie. Lane0=X0Y8, Lane7=X0Y15.

  For the X4 design, I tried Lane0=X0Y15-Lane3=X0Y12 and Lane0=X0Y8-Lane3=X0Y11 with no results. The board is in the same host that links at X8.

 

  I chipscoped several core signals and look fine, except that trn_lnk_up_n never asserts.

  ltssm=5, goes from 2, 4, 5 (polling.configuration), 0x2d and back to 2.

  trn_rst_n=1

  plllkdet=4'bf

  rxN_elec_idle=4'b0

  lane_reversal=2'b0

  clock_locked=1'b1

  mmcm_locked=1'b1

  gt_pll_lock=1'b1

  trn_lnk_up_n=1'b1

 

  I suspect the issue would be getting the right lane0 into the right GTX, but have no insight how to 'find' lane0, other than trial and error?

 

Any ideas will be appreciated.

-Pat

 

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patocarr
Teacher
Teacher
7,555 Views
Registered: ‎01-28-2008

Hi all,

 

  I submitted this case to Xilinx support, and they provided a workaround that will be fixed in a future software version.

 

  Basically it requires manually editing the routed ncd netlist with FPGA Editor to set to FALSE the RCV_TERM_VTTRX, RCV_TERM_GND attributes in the GTXs that are present in the PCIE lanes but not instantiated by the PCIE core, ie. the 7 lanes that aren't used by the X1 lane design but are electrically connected to the PCIE connector.

 

  Kudos to luisb to help me get through this!

 

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

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luisb
Xilinx Employee
Xilinx Employee
6,368 Views
Registered: ‎04-06-2010
Have you tried using an interposer when you try to train down to a x4 or x1? Or have you tried taping off the unused lanes so that they are electrically unconnected.

Let us know if this makes a difference.
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deepeshm
Xilinx Employee
Xilinx Employee
6,358 Views
Registered: ‎08-06-2008

The link below shows how to tape off the lanes:

http://www.xilinx.com/support/answers/38988.htm

 

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patocarr
Teacher
Teacher
6,333 Views
Registered: ‎01-28-2008

Thanks for the quick responses.

 

I've tried the X8 core with a X1 adapter that only connects lane0. It's like taping off the high lanes. It links ok and, as expected, the rxN_elec_idle are all high except lane0.

 

What can I probe to see why the ltssm doesn't seem to be receiving TS2s, thus not moving forward the fsm?

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patocarr
Teacher
Teacher
6,325 Views
Registered: ‎01-28-2008

I've also tested the X1 core design in an X8 lane adaptor and on an X1 lane adaptor. And this gets bizarre: the same X1 design links ok on the X1 lane adaptor, and it doesn't link on the X8 lane adaptor.

 

A data point that may be relevant, the X1 design in the X1 adaptor detected the partner as supporting gen2. But the X1 design on a X8 lane adaptor didn't. I assume this is due to the ltssm never reaching the polling.speed state.

 

Any other ideas?

 

Thanks in advance,

-Pat

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

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patocarr
Teacher
Teacher
7,556 Views
Registered: ‎01-28-2008

Hi all,

 

  I submitted this case to Xilinx support, and they provided a workaround that will be fixed in a future software version.

 

  Basically it requires manually editing the routed ncd netlist with FPGA Editor to set to FALSE the RCV_TERM_VTTRX, RCV_TERM_GND attributes in the GTXs that are present in the PCIE lanes but not instantiated by the PCIE core, ie. the 7 lanes that aren't used by the X1 lane design but are electrically connected to the PCIE connector.

 

  Kudos to luisb to help me get through this!

 

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

View solution in original post

0 Kudos