08-01-2018 04:32 PM
I'm trying to bring up a new board reusing a previously working Virtex 6 PCIE Gen1 x8 PCIe Core.
Going through AR# 34151 - (Design Assistant for PCI Express - Virtex-6 FPGA Integrated Block for PCI Express Link Up Debugging Diagram) yields 8b10b and disparity errors. (See attachment for chipscope results).
AR# 41151 - (Design Assistant for PCI Express - What happens if link has 8b10b errors?) indicates that this is likely signal integrity related.
Are there any Xilinx GTX parameters that can be changed that may help? Otherwise, do the symptoms pretty clearly point to a board layout problem?
I have already had the lane 1-7 TX coupling capacitors pulled from one of the boards under test but can't touch the host board.
08-02-2018 08:48 AM
08-03-2018 12:18 PM
The x8 core was generated in ISE 13.1.
It's not clear in the picture but the signal in chipscope is inverted and labeled ~TXELECIDLE I have captured the non-inverted signals in the captures attached to this post.
I generated a Gen1x1 core with similar results, however LTSSM isn't going into compliance now. Please see attached captures.
08-04-2018 02:18 PM
It looks like it went to polling.active and from there it went to detect. Perhaps it is not receiving what it should from the link partner to transition polling.configuration. Please refer to polling.active section in the PCIe spec.
Also, the following two documents might help in debugging the issue:
08-09-2018 09:46 AM
Thank you for the suggestion and additional debugging guides, particularly AR 56616 - PCIe Block Link Training Issues.
Given the 8b/10b and disparity errors and no real success with blindly modifying low level GTX settings and retesting it's probably time to look at the eye diagram.
Unfortunately, it will probably be some time before I can get track down the tools and resources to look into this further. Thank you for the support. I will try to post again when I have more results.
08-21-2018 03:30 PM