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Observer
Observer
4,065 Views
Registered: ‎05-12-2010

Virtex6 PCIe endpoint V1.4 simulation fail

I have generated PCIe endpoint V1.4 in ISE11.5, set 1 base address for 32 bits memory access, memory space set to 4MB;

others BAR are not used. then I try to run simulation of example design, it hang at memory write cycle. below listed the detail steps.

1. use default configuration space access in example and work fine.

2. Set base address 1 at 32'h1200_0000

3. Use task "board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_32" and try to access example design

4. the signal board.EP.core.trn_rbar_hit_n[6:0] never assert!!

 

 

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Xilinx Employee
Xilinx Employee
4,057 Views
Registered: ‎08-07-2007

Hi,

 

Make sure that you are also setting the memory enable bit in the command register located at address 0x04 in the PCI configuration space. Its bit 1 of this register. If you do not set that bit then the core will not claim incoming memory transactions.

 

Regards

John

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Xilinx Employee
Xilinx Employee
4,014 Views
Registered: ‎04-06-2010

What simulator are you using?

And are you using the example scripts that are provided with the core?

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