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Explorer
Explorer
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Registered: ‎12-06-2013

What is the MSI-X interface for? V7 Gen3

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Config: V690T, PCIe gen3, v1.6 of the core, Core Gen
 
Early in the design I thought that using the MSI-X port on the core would simplify sending interrupts from an endpoint configuration. Looking at the port now I don't understand what the port is for. Using PG023 v1.4 (p55-56). Here is what the manual says: 
 
1. The cfg port implies that you can pass the address and data of an MSI-X interrupt and the core will handle the transmitting for you. PG023 (p55-56)
2. Table 3-13 says that you cannot use this port for MSI-X and that you have to send the MSI-X through the RQ path as a memory write transaction. PG023 (p155, says it twice, once in the table and once in the last paragraph of the page.
3. PG023 shows a timing diagram of the MSI-X configuration port being used on p158.
 
So, I need MSI-X to work for my implementation but it is unclear on whether or not I can use the configuration interface the product guide talks about. It would simplify my design if the interface works.
 
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Explorer
Explorer
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Registered: ‎12-06-2013

Re: What is the MSI-X interface for? V7 Gen3

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I would just like to finish this post up and mention that Xilinx has resolved this issue by saying:

 

You will want to follow the information NOT on page 166. You will only need to use the cfg_interrupt_msix_* interface and you will not need to generate your own MWr in order to do a MSI-X interrupt. 

 So.....from a post I made earlier where I was sure this was the case PCIe gen3 Virtex 7 MSI-X datasheet correction , it is still true :)

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Explorer
Explorer
14,358 Views
Registered: ‎12-06-2013

Re: What is the MSI-X interface for? V7 Gen3

Jump to solution

I would just like to finish this post up and mention that Xilinx has resolved this issue by saying:

 

You will want to follow the information NOT on page 166. You will only need to use the cfg_interrupt_msix_* interface and you will not need to generate your own MWr in order to do a MSI-X interrupt. 

 So.....from a post I made earlier where I was sure this was the case PCIe gen3 Virtex 7 MSI-X datasheet correction , it is still true :)

View solution in original post

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