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cgmAether
Observer
Observer
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Registered: ‎06-05-2020

What options are available for sharing a single PCIe port with two discrete applications on one FPGA(Alveo U200)?

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Preface: We have an Alveo U200 that we would like to run two discrete applications on. These applications are prebuilt and we would like to change as little as possible on each of them. Both applications interact with the PCIe through different methods. We would like the ability to switch which application has access to the PCIe. The applications never need to use the PCIe simultaneously.

Application A: Uses PCIe through the Xilinx IP 'DMA/Bridge Subsystem for PCI Express (PCIe)'. Application A's internals can more easily be modified.

Application B: Uses PCIe through a custom-built PCIe communication module. Ideally, Application B's internals should not be altered.

Question 1: What options are available in the Xilinx flow or Xilinx IP Catalog that will allow us to switch which application has access to the PCIe? 

Question 2: For Application B, is there any way to access the PCIe IP that is within the DMA/Bridge Subsystem for PCI Express (PCIe) IP?

Question 3: Is there any way to send raw tlp packets to the Host through the DMA/Bridge Subsystem for PCI Express (PCIe) IP if we cannot access the internal PCIe module? In our case, when Application B is active, we need the FPGA to send raw tlp packets to the connected host without the host having to request or send anything. 

My attempts: In application A in the DMA/Bridge Subsystem for PCI Express (PCIe) module, I expanded the output pin, 'pcie_mgt', and attempted to wire each of the 4 outputs into multiplexers or de-multiplexers depending on if they were input or output. Then, I created a simple module that recombines these 4 wires back into a single 32 bit wide wire. I am unable to connect this recombined wire to the final output pin 'pci_express_x8'.

Question 4: What constraints exist on this output pin and how can I fulfill them? If I am unable to rewire the output in this way, are there any other ways that I can successfully share PCIe access between applications?

 

Any help is appreciated, thanks!

 

Included are screenshots of the block diagram of Application A, where I attempted to rewire the output of the Xilinx IP.

UpdatedXilinxForumAetherArgus.PNG

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deepeshm
Xilinx Employee
Xilinx Employee
582 Views
Registered: ‎08-06-2008

Not clear if you are trying to share the PCIe IP also or just the GTs. If it is PCIe IP, there isn't a way to access PCIe hard block in the XDMA IP. If it is GT that you are trying to share, you might be able to do mux/de-mux but I don't see this being straight forward; theoretically, might be doable. You might run into implementation limitations. If it is PCIe IP that you are trying to share between the two applications, maybe you could use the base IP (i.e. only th PCIe hard block) and do mux/de-mux on the user interface side of the PCIe hard block to share the IP between your applications. Now, with this approach you will need to implement your own XDMA engine. 

The above is just a thought; the use case is not something that we support or have tested. 

Thanks. 

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deepeshm
Xilinx Employee
Xilinx Employee
583 Views
Registered: ‎08-06-2008

Not clear if you are trying to share the PCIe IP also or just the GTs. If it is PCIe IP, there isn't a way to access PCIe hard block in the XDMA IP. If it is GT that you are trying to share, you might be able to do mux/de-mux but I don't see this being straight forward; theoretically, might be doable. You might run into implementation limitations. If it is PCIe IP that you are trying to share between the two applications, maybe you could use the base IP (i.e. only th PCIe hard block) and do mux/de-mux on the user interface side of the PCIe hard block to share the IP between your applications. Now, with this approach you will need to implement your own XDMA engine. 

The above is just a thought; the use case is not something that we support or have tested. 

Thanks. 

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cgmAether
Observer
Observer
528 Views
Registered: ‎06-05-2020

We tried to work with the below block diagram, but get errors about the pcie_mgt pins being unroutable. I assume there is no way to put logic in between the xdma modules and the pcie output pins when you actually implement these components onto on board transceivers.

finalDesign.png

 

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