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Anonymous
Not applicable
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Where is the reference CLK in the PCIE design

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I couldn't find the diff  signal refclk+ and refclk- in the pcie core  interface. Is it the refclkout  ? And why it's only a single   signal in the interface?I think the PCIE signals in the core interface should be mapped to the fpag pins  directly.

  Did i figure it out?

 

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luisb
Xilinx Employee
Xilinx Employee
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Registered: ‎04-06-2010

Look into the example design and the pins are called sys_clk_p and sys_clk_n.  These clocks go to a differential input buffer that eventually goes to the PCI Express core.

 

Here's what you'll see in the xilinx_pci_exp_ep.v:

  IBUFDS refclk_ibuf (.O(sys_clk_c), .I(sys_clk_p), .IB(sys_clk_n)); 

 

Then sys_clk_c goes to the sys_clk input of the core.

 

The code may be different if you're targeting different devices, but I think you should get the point.

 

Hope this helps.

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luisb
Xilinx Employee
Xilinx Employee
5,271 Views
Registered: ‎04-06-2010

Look into the example design and the pins are called sys_clk_p and sys_clk_n.  These clocks go to a differential input buffer that eventually goes to the PCI Express core.

 

Here's what you'll see in the xilinx_pci_exp_ep.v:

  IBUFDS refclk_ibuf (.O(sys_clk_c), .I(sys_clk_p), .IB(sys_clk_n)); 

 

Then sys_clk_c goes to the sys_clk input of the core.

 

The code may be different if you're targeting different devices, but I think you should get the point.

 

Hope this helps.

View solution in original post

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Anonymous
Not applicable
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Ok ,thanks. a lot I 've found it. And another question , the refclk+/-  is from host to fpga? or from fpga to host?  Iam confused by the information in web

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