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485 Views
Registered: ‎07-22-2019

Why I can't find the BMD testbench inside xapp1052 package?

I downloaded xapp1052.zip file, and ran the simulation in ModelSim. The DSport and tests only support PIO tests. Does xilinx provide any tests files or codes for BMD?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Please find attached unverified sample testbench for XAPP1052.

Please note this is not officially supported and is being provided here as a reference to build your own test bench. Let us know if it works for you. If you need to make any changes, please let us know those too so that others can benefit.

Thanks.

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Registered: ‎07-22-2019

Hi deepeshm,

 

Thanks for you reply. Now i can start DMA write from EP, and also i can see the data transmitted from EP at RP side. 

 

However, i have a doubt about your stimulus:

I can't simulate successfully except that i modified the routine from "board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000004, 32'h00000007, 4'b1110);" to "board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000001, 32'h00000007, 4'b1110);".

I did this modifcation for i searched from xilinx forum and found several posts discussing about this. And i was confused, why this setting was applied in different address?

https://forums.xilinx.com/t5/PCI-Express/in-simulation-BMD-Not-read-request-and-completions/m-p/177106

Above post used address "32'h00000004", and below post used address "32'h00000001".

https://forums.xilinx.com/t5/PCI-Express/Problems-of-PCIE-DMA-simulation/m-p/329263

 

I have aonther question: Dose above configuration used for RP side Bus Master Enable setting? If you want to use BMD, you don't only set EP side Bus Master Enabe, but also set RP side Bus Master Enabe. Am i right?

 

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