12-12-2018 11:43 PM
xdma Pcie gen2 x8 bandwidth is too low, how to increase bandwidth？
Operating environment as follows.
operating system：win10 1809.
Development environment：vivado2017.3, visual studio 2015
Driver version：xdma_driver_win_src_2017_4(Provided by Xilinx)
The xdma settings are as follows
The link is as follows，
Mainly running in c2h stream mode, normal situation due to XDMA_RING_BLOCK_SIZE, XDMA_RING_NUM_BLOCKS limit（dma_engine.h）, read data can only reach 1M, so I set XDMA_RING_BLOCK_SIZE to 512 * PAGE_SIZE, it can run normally
Xdma_rw.exe c2h_1 read 0 -l 104857600
The read time is too long.
Can't reach 4GB at all
How should I increase bandwidth?
12-20-2018 10:14 AM - edited 12-20-2018 10:15 AM
Few things to check.
1. Whether MPS of the link can be increased?
2. If you are using interrupt mode, can you try polling mode?
Following instructions from the readme.md file can be followed to try this.
### Poll Mode
The default mechanism for detecting a DMA transfer completion is the use of interrupts. However the driver also supports polling the hardware for completion instead. The use of poll mode may decrease DMA completion latency. This feature can be enabled at driver installation as follows:
1. Uninstall any currently installed XDMA driver.
2. Locate the *XDMA.inf* file in the driver package directory (*build/`ARCH`/XDMA_DRIVER/`CONFIG`*)
3. edit the following lines in the file as follows:
4. Install the driver using the device manager as normal.
Alternatively the *XDMA.inx* file in the driver source folder (*sys/*) can be edited in the same manner, however in this case a recompilation is required before the installation.
12-20-2018 11:26 AM
Can you try to upgrade to the latest Vivado release?
For driver also, we have a new driver -2018_2. Please check this also.
12-20-2018 05:30 PM
Thank you for your reply. Using vivado2018.3, and driver 18.2, there is no change under c2h in AXI stream mode.
Look at the driver's code and find that c2h is not the same as the read function called in axi_mem mode and axi_stream mode.
In axi-mem mode, the performance can reach 50%, but in axi-stream mode, it can only reach 5%.
I checked the driver print, the time spent on memory copy, why the stream mode needs to perform the memory copy in the driver. Shouldn't it be a direct mapping?
04-07-2020 01:12 AM
I am trying to use the PC to transfer data to the FPGA and receive it back via PCIe, I use the KC705 Kit and xdma axi stream mode, when the data transmission is 256MB or larger 2GB, the speed of H2C and C2H are only 200MB/s. I have used ila to check the data transfer under FPGA and found that after each sending a packet (tlast has a value of 1), the tvalid (h2c) assert 0 for a very long time (attached files). Do you know how this tvalid H2C is controlled by xdma? Is there any way to adjust the driver's code to reduce the tvalid time to a low signal?
Thank you very much.