cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
7,143 Views
Registered: ‎11-21-2009

Writing DATA from PCIe(ml555) Card to a File !!! I realy need help

Hello everybody,



1...........................................................................................................................
..........................................................................................................................
My first quastion is that:
In the latest version of Xapp1052(ML555) we have two prepared project, first one is
DriverMgr(VC++ for generating dll) and second GUI(VBasic generating exe file by mentioned dll).

I programed the board after designing and all things work fine now!
I would like to complete VBasic GUI in order to writing dma data from the card to a file saved in the PC.
so I added following line to the VBasic project :
..
..
..

Private Sub Command2_Click()

    Dim buf(200) As Byte
    Open "d:\DataFile.txt" For Output As #1
    For i = 0 To 100
    Reg_MyValue = driverMgr.GetRegister32(2)    '-----> Write DMA TLP Address
    'Reg_MyValue = driverMgr.GetRegister32(7)   '-----> Read DMA TLP Address
    Call MoveMemory(buf(0), (Reg_MyValue), 4)   '-----> we store contents of this address to a buffer with 200 bytes

    Call GetMem4((Reg_MyValue + i), A)             
    Print #1, A
    Next i
    Close #1
   
End Sub
..
..
..

When I read contents from this address(stored in Write DMA TLP Address Register), I will expect the
buf(200) to be fill of this pattern, which we have set in the GUI(Data Pattern Write register), but it isn't !!

should I set a continuse conter instead?
I wish to know how to know the address of writing of these data?

In dll project this function have 4 argument (Cs3_1000::SetDMAWrite(long size, long count, long pattern, long *status)),
while in the the VBasic project it have been calle with 3 argument from dll, like:
driverMgr.SetDMAWrite(CLng(txtTLP(0).Text), CLng(txtCount(0).Text), CLng("&H" + txtPattern(0).Text))
and I couldn't fill my file by calling this function.
..........................................................................................................................
..........................................................................................................................









2...........................................................................................................................
..........................................................................................................................

And the second quastion is setting a continous 32bit-counter in stead of pattern,
which place in the BMD_EP_MEM.v verilog module should write it:

Now I have written a counter in the BMD_EP_MEM.v module to be maped in one of core registers:


         case (a_i[6:0])
 
            7'b0000000: begin
            .....

           7'b0000001: begin
            .....     
   //--------------------------- my 32bit_counter ----------------- I added this part
  
               7'b010100: begin
                 rd_d_o <= {counter_32bit};
               end       
   //-------------------------------------------------------------
  
              // 50-7FH : Reserved
               default: begin
  
                 rd_d_o <= 32'b0;
                  end
               endcase
              end
          end
         ....
         ....              
        
And then I think that we should insert this counter into trn_td [63:0] in the "BMD_64_TX_ENGINE.V" in order to change
write data pattern to be our 32_bit counter, could you please show me which place I shoud insert it in the bellow
BMD_64_TX_ENGINE.V code? (counter then will be replaced by ADC data)

Bellow lines is contents of this module whitout modification:

              // PIO read completions always get highest priority
              if (req_compl_q &&  !compl_done_o &&  !trn_tdst_rdy_n && trn_tdst_dsc_n) begin
                trn_tsof_n       <= 1'b0;
                trn_teof_n       <= 1'b1;
                trn_tsrc_rdy_n   <= 1'b0;
                trn_td           <= { {1'b0},                   
                                      `BMD_64_CPLD_FMT_TYPE,
                                      {1'b0},
                                      req_tc_i,
                                      {4'b0},
                                      req_td_i,
                                      req_ep_i,
                                      req_attr_i,
                                      {2'b0},
                                      req_len_i,
                                      completer_id_i,
                                      {3'b0},
                                      {1'b0},
                                      byte_count };
                  

              end else if (mwr_start_i  &&  !mwr_done_o &&  serv_mwr &&  !trn_tdst_rdy_n &&  trn_tdst_dsc_n &&  cfg_bm_en) begin
 ..
                 trn_td           <= { {1'b0},
                                      {mwr_64b_en_i ?
                                       `BMD_64_MWR64_FMT_TYPE : 
                                       `BMD_64_MWR_FMT_TYPE},
                                      {1'b0},
                                      mwr_tlp_tc_i,
                                      {4'b0},
                                      1'b0,
                                      1'b0,
                                      {mwr_relaxed_order_i, mwr_nosnoop_i}, // 2'b00,
                                      {2'b0},
                                      mwr_len_i[9:0],
                                      {completer_id_i[15:3], mwr_func_num},
                                      cfg_ext_tag_en_i ? cur_wr_count[7:0] : {3'b0, cur_wr_count[4:0]},
                                      (mwr_len_i[9:0] == 1'b1) ? 4'b0 : mwr_lbe_i,
                                      mwr_fbe_i};
                      ..               
                      ..
                      ..

              end else if (mrd_start_i && !mrd_done &&  serv_mrd &&   !trn_tdst_rdy_n &&  trn_tdst_dsc_n &&  cfg_bm_en) begin     

                trn_td           <= { {1'b0},
                                      {mrd_64b_en_i ?
                                       `BMD_64_MRD64_FMT_TYPE :
                                       `BMD_64_MRD_FMT_TYPE},
                                      {1'b0},
                                      mrd_tlp_tc_i,
                                      {4'b0},
                                      1'b0,
                                      1'b0,
                                      {mrd_relaxed_order_i, mrd_nosnoop_i}, // 2'b00,
                                      {2'b0},
                                      mrd_len_i[9:0],
                                      {completer_id_i[15:3], mrd_func_num},
                                      cfg_ext_tag_en_i ? cur_rd_count[7:0] : {3'b0, cur_rd_count[4:0]},
                                      (mrd_len_i[9:0] == 1'b1) ? 4'b0 : mrd_lbe_i,
                                      mrd_fbe_i};
                      ..               
                      ..
                      ..
                  trn_td           <= { req_rid_i, req_tag_i,  {1'b0}, lower_addr,   rd_data_i };   // comment by am:   rd_data_i[31:0] is all Mem Regs
                   ..
                  trn_td           <= {{tmwr_addr[31:2], 2'b00}, mwr_data_i_sw};
                   ..
                  trn_td           <= {{24'b0},mwr_up_addr_i,tmwr_addr[31:2],{2'b0}};
                   ..
                  trn_td           <= {mwr_data_i_sw, 32'hd0_da_d0_da};
                   ..
                  trn_td           <= {mwr_data_i_sw, mwr_data_i_sw};
                   ..  
                  trn_td           <= {{tmrd_addr[31:2], 2'b00}, 32'hd0_da_d0_da};
 
..........................................................................................................................
..........................................................................................................................




I'll appreciate you answer my quastions, it's very urgent for me just now !!!
Thanks you in advance !!!
0 Kudos
7 Replies
Highlighted
Visitor
Visitor
7,118 Views
Registered: ‎11-21-2009

 

Could you please help, it's urgent?

 

Did someone transmit  dma data  to a file? 

0 Kudos
Highlighted
Participant
Participant
7,113 Views
Registered: ‎09-18-2009

1. Is your card recognized, opened properly?

(CreateFile returning a valid handle)

 

2. If you write to a register  address and read back the value; do they match?

 

 

0 Kudos
Highlighted
Visitor
Visitor
7,109 Views
Registered: ‎11-21-2009

My card is recognised and opened. and I'm compiling all lines of VBasic project and I can call all those function from it's dll.
I've could write and read to/from all physical memory registers in core and when I read back all values, they are match with
every things which I wrote.
In the new version of xapp1052, dll and exe code project are abailable and we can compile and then open the driver and call

all functions easily.
but I don't know why, when I set a pattern to the write pattern register in order to send TLP's of that pattern to specific place

of pc memory or ram (although we have address of pc memory in write address register) I can not see desired size or value !!?
I got disoppointed.

0 Kudos
Highlighted
Participant
Participant
7,102 Views
Registered: ‎09-18-2009

So you busmaster some packets from the card to the PC RAM, and they don't arrive?

 

I can't help you with xapp specific problems, as I'm not using it. (we are writing our own stuff), but

you should try and check with chipscope that the packets are actually sent and the memory address of the TLP is right...

0 Kudos
Highlighted
Visitor
Visitor
7,099 Views
Registered: ‎11-21-2009

I did't change original verilog or GUI code and we should except to see correct pattern in value of "write address register" lacated in pc ram,

after setting pattern and start dma.

do chiposcop show us address of pc memory(ram) and it's values?

 

0 Kudos
Highlighted
Participant
Participant
7,095 Views
Registered: ‎09-18-2009

Using the right trigger and data you can see the bus-master TLP packets (DMA write) content.

(try triggering the trn_tsof/trn_td first...)

 

There is a value in the packet header which specifies the address where to write it (in PC RAM). If thats OK, then the error could be on the driver or the application level...

0 Kudos
Highlighted
Visitor
Visitor
7,061 Views
Registered: ‎11-21-2009

I really "thank you" lacirta for your usefull comments,

I'll try act like your suggest(debuging with chiposcope) and I hope to do my best.

 

 

0 Kudos