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Observer
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Registered: ‎12-04-2019

Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Hello 

How does one write the descriptors to the H2C and C2H channels in the bypass mode. I have enabled the channel bypass interfaces in Vivado, but not able to find how and where to write the descriptors from the PL side. Any help would be great!

Regards

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Observer
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Registered: ‎12-04-2019

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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I figured out a way to get the descriptor bypass mode working. I found the descriptor bypass ports in the design.vhd file and edited using an external editor and changed the source and destination address, control and length and generated the bitstream. Writing to the appropriate registers in SDK worked perfectly for me.

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-09-2019

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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The Descriptor Bypass is explained in PG195 on page 26.

Please check the descriptor is being sent on the correct bus (c2h_dsc_byp / h2c_dsc_byp) and all control register bits are set correctly.

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Observer
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Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Hello @mmcnicho 

Thank you for the reply. I have read through the documentation. I am not able to understand how to send descriptors to the channels. Currently, I am using Stream FIFO to write to the channels. Is that alright or do you any other suggestions. Are the channels memory mapped so that I can write to their registers using the offsets given in the documentation?

Regards

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Registered: ‎05-02-2017

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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hi @naarayananrao ,

 

Thanks for contacting xilinx  forums ,

Isee your looking for sample code , you generate the example design with the AXI4-Memory Mapped with Descriptor Bypass Example in vivado.

When Descriptor bypass mode is enabled, the user logic is responsible for making descriptors and transferring them in descriptor bypass interface. Mapped design with descriptor bypass mode enabled. You can select which channels will have
descriptor bypass mode. When Channel 0 of H2C and Channel 0 C2H are selected for Descriptorbypass mode, the generated Vivado example design has descriptor bypass ports of H2C0 andC2H0 connected to logic that will generate only one descriptor of 64bytes. The user is responsible for developing codes for other channels and expanding the descriptor itself.

 

Let me know your inputs

 

chandra 

Regards
Chandra sekhar
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Observer
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Registered: ‎12-04-2019

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Thank you @csattar 

I have enabled the channel 0 of H2C as I need only H2C transfer. I have enabled and configured everything what the descriptor bypass example design suggests. My question is how to pass the 64 byte descriptor? Should I do it from the SDK or from Vivado? Should I use any IP blocks to do that or should I just write to it?

If yes, then what is the base address and offset address for these channels and what is the procedure to send the descriptors. Can you please explain in detail.

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Observer
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Registered: ‎12-04-2019

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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I figured out a way to get the descriptor bypass mode working. I found the descriptor bypass ports in the design.vhd file and edited using an external editor and changed the source and destination address, control and length and generated the bitstream. Writing to the appropriate registers in SDK worked perfectly for me.

 

 

View solution in original post

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Registered: ‎06-29-2018

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Hi,

I had generated the example design with descriptor bypass mode enabled and saw the codes. I have built upon that logic to support multiple descriptor loading based on register configurations.

In the example design, I did not understand how the run bit for the H2C engine and C2H engine is in the control register is handled.

Is the bit set from host side or the bit has to be set from the RTL side using the AXI-L slave interface for XDMA configuration, also can we keep the run bit always set, I want the engines to be ready always to take the descriptors as and when we load it?

I am trying to communicate with another FPGA in the PCIe network which has XDMA core. The Root complex gives the PCIe BAR address of the other FPGA

when I load the XDMA with the following configuration,  the DMA engine stalls, and becomes unusable, the status bit says busy and never comes to IDLE

h2c_dsc_byp_src_addr_0 = PCIe address of FPGA 2

h2c_dsc_byp_dst_addr_0 = internal Memory address of FPGA 1

h2c_dsc_byp_len_0 = 28'd1024

h2c_dsc_byp_ctl_0 = 16'd2

h2c_dsc_byp_load_0 = 1'b1

Can someone give a suggestion on this?  is Endpoint to Endpoint communication supported by XDMA? what should be the host/destination address when using H2C or C2H descriptor bypass interfaces? should the address be added with the PCIe BAR address allocated by the Root complex?

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Observer
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Registered: ‎12-04-2019

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Hello @shahbaz_coreel 

Apologies for the late reply. You have to set the DMA Engine bit from the FPGA/RTL Side. And the h2c_dsc_byp_ctl_0 should be set to 16'h03 I believe (it was mentioned in the example design for the XDMA).

Regarding the second part of your question, I haven't done it like that, but I believe you have to give the source address of the descriptors for both H2C and C2h as mentioned in Page 67 to Page 74 in the XDMA manual : https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_1/pg195-pcie-dma.pdf and then you have to set the Control bit to start the transfer.

 

Let me know if this helps!

Regards

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Registered: ‎06-29-2018

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Hi, Thanks for your reply,
I was able to do the descriptor bypass transfer successfully from one FPGA to another.
I created the descriptor such that the destination address is the PCIe DMA Bypass BAR of FPGA2 added with its internal address and Source address as the internal address of FPGA1 (Trying C2H desc bypass)
I enabled XDMA C2H engine run bit using the AXI-L slave interface from RTL and loaded the descriptor with h2c_dsc_byp_ctl_0 = 16'h03, and desired transfer length.
I was able to see the read activity in the AXI MM read interface of FPGA1 and AXI MM Bypass write interface in FPGA2.
Thanks for the support:
I also used this piece of code i found on Github for loading descriptors:
https://github.com/rsarwar87/xdma_dsc_byp_cltr
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Observer
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Registered: ‎12-04-2019

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Thank you very much Shahbaaz. Unlike you I was using a naive approach to control the Descriptors. Your code really helps. I am trying to control the IP using the Microblaze to write to the Descriptor Bypass Interface. Will let you if it works.

 

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Registered: ‎06-29-2018

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Good to know that there are multiple options now, keep updating. 

PS: That code is not mine, I had implemented a similar logic for loading descriptors as per my application!

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Observer
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Registered: ‎12-04-2019

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Quick question: How do I get to control those bits in the RTL IP. Can I map an address to it?

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Registered: ‎06-29-2018

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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if you are referring to the XDMA registers (run bit), you can use the AXI lite slave interface of XDMA to control that!

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Registered: ‎06-29-2018

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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or if you are referring to the descriptor bypass controller IP, yes you can map any address to it,
I just used the bypass controller code and mapped the required fields to my own register bank which is configured via the XDMA AXI-L master interface
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Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Got it thanks for the references.

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Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Hello @shahbaz_coreel 

The IP isn't working for me. I am not able to set the control bits given at the offset 0x1C. Any ideas about this and are we supposed to the RTL code for the user logic to forward the address to the XDMA descriptors or is it readily available in the code given in the repo?

 

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Registered: ‎06-29-2018

Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Hi,

The IP is just a module to load the descriptors into the descriptor bypass interface of the XDMA, it is up to the user to give all the necessary inputs it requires for loading the descriptor, additionally, it allows for repeated descriptor loading. As far as the configurations are concerned, I did not face any issue there, if the mapping is done properly you should be able to configure all the registers.

I suggest you create an example design with descriptor bypass mode enabled and AXI-L master interface enabled, and the DMA bypass interface also enabled.

You can replace the logic of generating descriptor in the example design with this IP core (Top file with AXI interface).

Connect the AXI interface of this IP to the AXI-L master interface of XDMA, then you will be able to control the IP using the commands available for reg_rw  in the XDMA Driver. also before loading the descriptor, you can set the run bit of the corresponding engine using the xdma_control application available with the driver.

You can verify the descriptor completion using the same xdma_control application to read the status of the XDMA engines.

 

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Re: Writing Descriptors to the channels in Descriptor Bypass mode - XDMA

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Thanks for the reply, @shahbaz_coreel . I am connecting the AXI slave interface given in the IP to the Microblaze. I am not using any drivers as I don't want the host to be involved here. I am trying to write the Descriptor parameters from the Microblaze, which I have done without any problems to the respective register space. 

The only issue I am facing is writing the Control register of the IP mapped at the offset 0x1C, where the bits 30-4 are reserved and the last 3 are used to issue the descriptors to the bypass interface of the XDMA IP. I am not able to set the last 3 bits of the IP and don't know whats the problem there. I am not changing anything in the code as it best fits my application.

P.S. I am programming in C using the SDK. Any help would be great!

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