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Observer
Observer
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Registered: ‎08-07-2017

XAPP1171 DMA to ZC706 DDR PCIe endpoint

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Below is a ZC706 PCIe endpoint board design. The design is based on XAPP1171, where I have added the Zynq PS to allow DMA from a host to the endpoint DDR memory, which in this case is the PS DDR3 memory (I believe).

 

On the host system, I have developed the driver which is able to map the BARs. In the end, I am able to write some data to 0x00100000, which I believe is the PS DDR3 memory on the ZC706 endpoint, and retrieve the correct data from that location. 

However, I have implemented some bare metal code to verify the writes to the PS DDR3 memory from the host. Reading from 0x00100000 did not yield the same value I have written from the host to the endpoint. This was done using:

 

Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR,0x00).

 

XPAR_PS7_DDR_0_S_AXI_BASEADDR is set to 0x00100000 in xparameters.h.

 

Am I suppose to see any changes by writing to 0x00100000 from the host to PS DDR3 memory by implementing the above bare metal code? I have attached the board design and address map below, which may prove useful for answering the question.

 

Regards

Andrewboard design

address map

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Observer
Observer
3,983 Views
Registered: ‎08-07-2017

Given the lack of feedback on Xilinx forums, I have found that you need to enable the data and instruction cache in the SDK, then disable it after read/write to DDR memory. I'm guessing Xil_In/Out32 reads from these caches and thus it did not see an updated value as the caches were not enabled. An example of the cache code is pasted below.

 

Xil_ICacheEnable();
Xil_DCacheEnable();

 

xil_printf("writing to 0x%x\n\r",XPAR_PS7_DDR_0_S_AXI_BASEADDR);
Xil_Out32(XPAR_PS7_DDR_0_S_AXI_BASEADDR,0x1234); 
xil_printf("read at 0x%x: 0x%x\n\r",XPAR_PS7_DDR_0_S_AXI_BASEADDR,Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR));

 

Xil_DCacheDisable();
Xil_ICacheDisable();

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Highlighted
Observer
Observer
3,984 Views
Registered: ‎08-07-2017

Given the lack of feedback on Xilinx forums, I have found that you need to enable the data and instruction cache in the SDK, then disable it after read/write to DDR memory. I'm guessing Xil_In/Out32 reads from these caches and thus it did not see an updated value as the caches were not enabled. An example of the cache code is pasted below.

 

Xil_ICacheEnable();
Xil_DCacheEnable();

 

xil_printf("writing to 0x%x\n\r",XPAR_PS7_DDR_0_S_AXI_BASEADDR);
Xil_Out32(XPAR_PS7_DDR_0_S_AXI_BASEADDR,0x1234); 
xil_printf("read at 0x%x: 0x%x\n\r",XPAR_PS7_DDR_0_S_AXI_BASEADDR,Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR));

 

Xil_DCacheDisable();
Xil_ICacheDisable();

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