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Visitor
Visitor
8,155 Views
Registered: ‎11-12-2009

XAPP859 on XC5VLX110T

Hi,

 

I'm trying to get xapp859 synthesized for an XUPV5-110T board, but xapp859 targets 50T. Is there an easy way to port the design to 110T? My naive attempt was to simply change the target device to XC5VLX110T in ISE 11.3, but the design does not meet timing. I assume this is because the constraints file is no longer valid due to pin rearragnements between 50T and 110T.

 

Thank you in advance for any help or insight.

 

J

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Mentor
Mentor
8,121 Views
Registered: ‎01-28-2008

I would say that you may get better timing if you also re-generate the PCIE netlist for that architecture. I don't recall seeing architecture-specific placement in the ucf, so the source code should be pretty portable. In my experience compiling for SX95T, LX110T & FX100T, the timing always is very tight in the Block Plus core; sometimes requiring manual placement of a handful of FFs. On very big designs (>75%) the PCIE core is always what fails timing first. I generate a full placement ucf of a successful build, and use it on subsequent builds to help maintain timing. PlanAhead exports IPs as netlist and placement.

HTH,
-Pat
https://tuxengineering.com/blog
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Visitor
Visitor
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Registered: ‎05-20-2010

hi all!
 I ported 50t to ml110t,I changed all the property to 110t,but at last I came across a error when promgen bit stream.Error as follows:
[root@localhost bit_prom_files]# promgen -w -p mcs -c FF -o ./xapp859_ml505.mcs  -ver 2  ./xapp859_ml505.bit -ver 3  ./xapp859_ml505.bit  -x  xcf32p
Release 10.1.03 - Promgen K.39 (lin)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
0x400000 (4194304) bytes loaded up from 0x0
ERROR:Bitstream:24 - Load address 0x400000 is above the maximum load address of
   0x3fffff.
ERROR:Bitstream:25 - 0x400000 bytes loaded up from 0x400000 would exceed
   promsize 0x400000.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
the ml505 ucf file is same with ml110t ucf file. So I think the ucf file  and source code should be pretty portable.it needn't change.
did you hava encounter this problem ? hope you help.
thank you!

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Xilinx Employee
Xilinx Employee
7,608 Views
Registered: ‎04-06-2010

Have you tried using the UCF from the XUPV5-LX110T Reference Design Page?

There you'll find a PCI Express x1 reference design.

 

The only constraints from the UCF that are required are:

 

INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y2;

 

NET  "sys_clk_p"       LOC = "AF4"  ;
NET  "sys_clk_n"       LOC = "AF3"  ;
INST "refclk_ibuf"     DIFF_TERM = "TRUE" ;

 

NET  "sys_clk_p"       LOC = "AF4"  ;

NET  "sys_clk_n"       LOC = "AF3"  ;

INST "refclk_ibuf"     DIFF_TERM = "TRUE" ;

 

NET "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out" TNM_NET = "MGTCLK" ;

TIMESPEC "TS_MGTCLK"  = PERIOD "MGTCLK" 100.00 MHz HIGH 50 % ;

 

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Visitor
Visitor
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Registered: ‎05-20-2010

 

Hi
I modified the ucf with 
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y2;
the error also emerge:
0x400000 (4194304) bytes loaded up from 0x0
ERROR:Bitstream:24 - Load address 0x400000 is above the maximum load address of
   0x3fffff.
ERROR:Bitstream:25 - 0x400000 bytes loaded up from 0x400000 would exceed
   promsize 0x400000.
I hava compared the ml110t pcie reference design ucf with xapp859 ucf.
110t reference design ucf:
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst"      LOC = RAMB36_X3Y9 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y13 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y12 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y11 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y10 ;
these are different with xapp859 demo.
In xapp859 ucf file,LOC=RAMB36_X1Y5,RAMB36_X1Y6,RAMB36_X1Y7,RAMB36_X1Y8,RAMB36_X1Y9
and "sys_reset_n" is also different.
I have try to modify the loc of "sys_reset_n" to "AC24". but come with many errors.
So should I modify other INST and NET locations now ?
thank you!

 

Hi

I modified the ucf with INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y2;the error also emerge:
0x400000 (4194304) bytes loaded up from 0x0
ERROR:Bitstream:24 - Load address 0x400000 is above the maximum load address of
   0x3fffff.
ERROR:Bitstream:25 - 0x400000 bytes loaded up from 0x400000 would exceed
   promsize 0x400000.

I hava compared the ml110t pcie reference design ucf with xapp859 ucf.
110t reference design ucf:INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst"      LOC = RAMB36_X3Y9 ;INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y13 ;INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y12 ;INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y11 ;INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y10 ;
these are different with xapp859 demo.In xapp859 ucf file,LOC=RAMB36_X1Y5,RAMB36_X1Y6,RAMB36_X1Y7,RAMB36_X1Y8,RAMB36_X1Y9
and "sys_reset_n" is also different.
I have try to modify the loc of "sys_reset_n" to "AC24". but come with many errors.
So should I modify other INST and NET locations now ?
thank you!

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Xilinx Employee
Xilinx Employee
7,454 Views
Registered: ‎09-02-2009

Hi Ninja,

 

The error message you are seeing has nothing to do with the design constraints . . . I think it is due to the size of the bitstream.  Does your script run 'promgen'?  If so, you'll want to make sure you are targeting the proper size prom.

 

Jason

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Visitor
Visitor
7,424 Views
Registered: ‎05-20-2010

hi Jason

thanks for your suggestion. I think you are right.

but i use impact tool to make bit file to ace file,start with cf card, at last it works.

 

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