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Adventurer
Adventurer
1,601 Views
Registered: ‎10-29-2017

XAZU5EV PCIe

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Hi,

   I tried to configure PCIe to device/Port type to Root complex with X2 lane, Gen-3. When I configured PCIe, I'm getting this error. Can you please help me how to overcome this error?

  • [Common 17-70] Application Exception: Failed to create subcore IP 'PCIE_BD_pcie4_uscale_plus_0_1_gt'. IP name 'PCIE_BD_pcie4_uscale_plus_0_1_gt' is already in use in this project. Please choose a different name.

  • [IP_Flow 19-1747] Failed to deliver file 'c:/vivado_18_2/Vivado/2018.2/data/ip/xilinx/pcie4_uscale_plus_v1_3/elaborate/gtwizard_elaborate_uscale_plus_v1_3.xit': ERROR: [Common 17-70] Application Exception: Failed to create subcore IP 'PCIE_BD_pcie4_uscale_plus_0_1_gt'. IP name 'PCIE_BD_pcie4_uscale_plus_0_1_gt' is already in use in this project. Please choose a different name.

    I'm facing this issue only in Zynq series and the device/Port type is automatically changing to 'EndPoint' device. I dont know why it is happening. Can anyone please help on this?

  

Xilinx issue.png
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Moderator
Moderator
1,447 Views
Registered: ‎02-11-2014

Re: XAZU5EV PCIe

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Hello @sumaiya,

I have attached a formal patch with this reply that will enable you to use the XAZU5EV-SFVC784-1Q-q with the UltraScale+ Integrated Block IP in Vivado 2018.2. Please let me know if you have any issues with it. AR71718 will be released to the public shortly to document the patch formally.

Vivado 2018.3 is expected to be released sometime in December.

Thanks,
Cory

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17 Replies
Moderator
Moderator
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Registered: ‎02-11-2014

Re: XAZU5EV PCIe

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Hello @sumaiya,

 

Which specific Zynq device are you using in Vivado 2018.2?

 

Thanks,
Cory

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Adventurer
Adventurer
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Registered: ‎10-29-2017

Re: XAZU5EV PCIe

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Device name  : XAZU5EV-SFVC784-1Q-q. When PCIe Port type is set to 'End Point/Root complex', first time it shows the following error: 

[IP_Flow 19-3461] Value '16' is out of the range for parameter 'User data width(TX_USER_DATA_WIDTH)' for IP 'design_1_pcie4_uscale_plus_0_2/design_1_pcie4_uscale_plus_0_2_gt' . Valid values are - 32, 64

Next time, following errors are repeated again and again

[Common 17-70] Application Exception: Failed to create subcore IP 'PCIE_BD_pcie4_uscale_plus_0_0_gt'. IP name 'PCIE_BD_pcie4_uscale_plus_0_0_gt' is already in use in this project. Please choose a different name.

[IP_Flow 19-1747] Failed to deliver file 'c:/vivado_18_2/Vivado/2018.2/data/ip/xilinx/pcie4_uscale_plus_v1_3/elaborate/gtwizard_elaborate_uscale_plus_v1_3.xit': ERROR: [Common 17-70] Application Exception: Failed to create subcore IP 'PCIE_BD_pcie4_uscale_plus_0_0_gt'. IP name 'PCIE_BD_pcie4_uscale_plus_0_0_gt' is already in use in this project. Please choose a different name.

 

But IP is generated successfully for the part number 'XCZU5EV-SFVC784-1Q-q' and 'XAZU5EV-SFVC784-1LV-i' .

How lane width and link speed is related to speed grade(-1) and temperature grade(Q/I)?  



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Moderator
Moderator
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Registered: ‎02-11-2014

Re: XAZU5EV PCIe

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Hello @sumaiya,

 

I have reproduced the issue you have reported with a XAZU5EV-SFVC784-1Q-q. I have filed a Change Request to get this issue resolved in a future release of Vivado.

Thanks,

Cory

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Adventurer
Adventurer
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Registered: ‎10-29-2017

Re: XAZU5EV PCIe

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Hi Coryb,

        Thanks for your co-operation. As per the project requirement, PCIe block (Root Complex with x2 @ Gen 2) need to be generated for the device number 'XAZU5EV-SFVC784-1Q-q'. 

        I kindly request you to provide solution on this.

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Moderator
Moderator
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Registered: ‎02-11-2014

Re: XAZU5EV PCIe

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Hello @sumaiya,

The Change Request has been resolved in Vivado 2018.3. We are currently working on a 2018.2 Patch so you can utilize the XAZU5EV-SFVC784-1Q-q in Vivado 2018.2 / UltraScale+ Integrated Blocks IP. Please give us a bit more time to complete this solution.

Thanks,
Cory

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Adventurer
Adventurer
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Registered: ‎10-29-2017

Re: XAZU5EV PCIe

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Hello @coryb

   Thanks for your support. When 2018.3 will get release? 

 

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Moderator
Moderator
1,448 Views
Registered: ‎02-11-2014

Re: XAZU5EV PCIe

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Hello @sumaiya,

I have attached a formal patch with this reply that will enable you to use the XAZU5EV-SFVC784-1Q-q with the UltraScale+ Integrated Block IP in Vivado 2018.2. Please let me know if you have any issues with it. AR71718 will be released to the public shortly to document the patch formally.

Vivado 2018.3 is expected to be released sometime in December.

Thanks,
Cory

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Adventurer
Adventurer
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Registered: ‎10-29-2017

Re: XAZU5EV PCIe

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Hello @coryb,

          Thank you. Will check and get back to you. 

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Moderator
Moderator
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Registered: ‎02-11-2014

Re: XAZU5EV PCIe

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Hello @sumaiya,

I am checking in to verify that the patch is working for your application. If it is, please mark the proper post as a solution. If not, please let me know so we can look into it.

Thanks,
Cory

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Adventurer
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Re: XAZU5EV PCIe

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Hi @coryb,
Can you please tell me how to use this patch?
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Moderator
Moderator
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Registered: ‎02-11-2014

Re: XAZU5EV PCIe

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Hello @sumaiya,

If you unzip the patch, it comes with a readme with instructions on how to apply it to your 2018.2 install. Let me know if you still have any questions on the patch install flow.

Thanks,
Cory

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Adventurer
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Registered: ‎10-29-2017

Re: XAZU5EV PCIe

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Hello @coryb,

          PCIe IP is generated with the required configuration. Thank you so much for helping.

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Adventurer
Adventurer
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Registered: ‎10-29-2017

Re: XAZU5EV PCIe

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Hello @coryb,

          After installing patch file, PCIe IP (End Point) which was generated in other projects earlier (before installing patch file) with part number XCVU9P are found to be locked. 

          Now, all Projects consists of PCIe IP need to be synthesized from first (as they are locked after installing patch file).

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Moderator
Moderator
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Registered: ‎02-11-2014

Re: XAZU5EV PCIe

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Hello @sumaiya,

This is expected behavior, since the patch you applied "uprev's" the IP. Did you apply the patch globally to your 2018.2 install (Method 1) or did you apply the patch using the user/project specific method (Method 2)

If you did Method 1, then ALL users using that specific 2018.2 build will get the patched IP and will need to update their IP accordingly.

If you did Method 2, then only users with the XILINX_PATH variable will have the patch applied. This is the favored approach for project specific users.

Thanks,
Cory

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Adventurer
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Registered: ‎10-29-2017

Re: XAZU5EV PCIe

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Okay, Thank you. I followed Method 1.

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Adventurer
Adventurer
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Re: XAZU5EV PCIe

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Hi Coryb, 

     In the same zynq device, XAZU5EV-SFV784-Q, Is it possible to have two PCIe RC in PL section? One PCIe with block location X0Y0, x2 @gen3 and another PCIe with block location X0Y1, x2 @gen3.

      When I tried to implement, Placement failed saying that it is incompatible with the device sometimes, sometimes implementation got successful. Can you please check on this and give me a clear idea on this? FYI, we have only one MGT bank in bank 224 where we have 4 MGTREFCLK pins and 8 transceiver pins. Is it really compatible? 

The error is : 

[Place 30-60] Place Check : This design requires more GTHE4_COMMON cells than are available in the target device. This design requires 2 of such cell types but only 1 compatible site is available in the target device. please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected.

How to overcome this issue?

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Moderator
Moderator
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Registered: ‎02-11-2014

Re: XAZU5EV PCIe

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Hello @sumaiya.

Thank you for posting your latest question in a new topic: https://forums.xilinx.com/t5/Implementation/Can-we-use-two-PCIe-with-two-block-locations-in-XAZU5EV/m-p/925640#M23282

I will take a look into this shortly.

Cory

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