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Registered: ‎01-17-2019

XC7Z015-485-2-GTP:how to make the IP core--AXI Memory Mapped To PCI Express use PLL1 which is one of the two clks( PLL0 or PLL1) from GT_COMMON.

I am now working on a project that needs to use clock signals of different frequencies generated in GTP_COMMON, and use PLL1 to the IP core AXI Memory Mapped To PCI Express, but the IP core seems to only use PLL0 clock from GT_COMMON by default, and i could not find the way to modify it, Is there anyone who can help me?

 

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