XDMA AXI-lite master ordering for double word transactions
The AXI-lite master interface in the XDMA that serves as a bypass to BAR0 is 32bit in size for data. If on the host the driver does an iowrite64 or an application does an 8byte write to some mmaped register, my presumption is that it gets translated into two discrete 4byte transactions on the AXI-lite interface since lite has a burst length of 1. In this case, is there a fixed ordering of whether the lower or upper word is written first?
Well, it's possible the core will reject 64 bit operations completely, which is allowed as per the PCIe spec (completer abort). If it doesn't, then presumably they will be handled in address order - lower address first, followed by upper address.