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henzer
Observer
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Registered: ‎04-06-2020

XDMA Bridge with NVME SSD Enumeration question

Hello,

I'm trying to enumerate and access a gen3 NVME SSD using a Microblaze-based design with XDMA Bridge in root port mode in a Virtex US+ FPGA.  I am trying to stream data using a DataMover with 128-bit wide M_AXI port connected to the S_AXI_B port on the XDMA bridge.  The Microblaze is running the endpoint enumeration example in the XilinxProcessorIPLib directory with some minor modifications.  See attached block diagram showing the DataMover and XDMA connections.  I'm using Vivado 2020.2 with 64-bit Ubuntu.

The link comes up correctly and the endpoint gets enumerated.  The default microblaze code was assigning a BAR0 address of 0x00001111 to the endpoint (not sure why such a non-aligned address...).  I changed this to write 0x0 to both the BAR0 and BAR1 address registers on the endpoint.  I also leave the default changes to the endpoint config register (bus mastering enabled, etc).  One more addition I made was to first write 0xffffffff to each of the two BAR address registers and read back the required size before setting each address to 0x0.  A screenshot of the Vitis console output is attached.

I would now like to access the Controller Registers described in section 3 of the NVME 1.3 spec.  I may be misunderstanding all of this BAR mapping, but I try to perform a 4-byte read at address 0x0 on the XDMA Bridge S_AXI_B interface, hoping to access controller register at offset 0x0.  I have a custom IP called stream_tester that supplies the commands to the DataMover.  I have an ILA on the signals between the stream_tester and DataMover as well as a System ILA on the connection between the DataMover and XDMA Bridge.  I see the traffic on the AR bus, but the XDMA Bridge returns a SLVERR condition.  I've attached screenshots of both ILAs capture for the attempted read.  FYI, I have "allow unaligned transfers" checked in the DataMover GUI, so I'm hoping I could still make a 32-bit read using the 128-bit-wide MM2S interface.

I also attached the relevant part of the IP Integrator address map.

Am I misunderstanding how the enumeration and/or bar mapping should be done?

Thanks for any help!

block_diagram.png
vitis_debug_output.png
ila1.png
ila2.png
address_map.png
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