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Visitor arminh
Visitor
409 Views
Registered: ‎03-25-2019

XDMA Credit mode, FIFO, …

First Thanks for every Answer.

Second here are some questions:

  1. The credit register is used to say how many descriptors the dma engine is allowed to fetch into it's
    FIFO or did i miss something? (Anwserd Indirect)

  2. What happens when the credits are zero? Does the engine stop or does it wait until it gets
    new credits to write/read again? (Anwserd)

  3. Is there a reason why there is no indicator how many descriptors the FIFO has fetched?

  4. How do i know if the FIFO of the engine is full? Or better how much it fetched.

  5. Can i update the descriptor list if the FIFO is stopped? (would need syncing i know)

  6. When can i set a new DESC address on the engine is that only a valid move if
    the engine is finished with the current descriptor chain?

  7. What's actually the major difference between sending multiple desc's alone with one having
    the stop bit set and sending chained descriptors?

  8. On page 18 of the pg195-pcie-dma there is a diagram of the internals of the xdma ip with
    the supplied driver attached now the rectangles are i suppose concurrent tasks so the dma
    has the descriptor fetch, the data fetch and the send all running async to each other? (Aka polling until a desc is there)

  9. Based on the previous question if it does that this then also means that if i get the completed IRQ
    it does not mean that the FIFO is finished on fetching the descriptors.

  10. Someone should look at page 41 as for sure i can translate but for me this seems to be incorrect:
    "The number of 'competed' descriptors up date by the engine after completing each descriptor in the list."

  11. Also someone mentioned that there is a write back happening to the dma desc memory is that correct and if so what
    is written back?

  12. I currently also don't get the RX of the example driver as it sets up only one transfer descriptor and retrieve's than
    X in size from it. Is the credit mode mandatory for using it? And when not how does one know many desc's the engine worked
    or is this stored in the completed_desc count? And are there no EOP indicators int the data stream on the RX side? I mean i get the size from
    the AXI-Ethernet but i'm curious if there is something like that.

  13. Is there a particular reason why there are only unchained transfers used inside of the refrence driver ?

  14. Should the last descriptor be empty or can i send a transmission without having a second descriptor that indicates the end?

  15. How big is the data fifo of the XDMA as i can only find the size for the desc fifo that is internally used.

  16. Also is there a way in software to set the "axi_aresetn" in software to high? (Aka reset IP's on Axi Bus)
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2 Replies
Xilinx Employee
Xilinx Employee
386 Views
Registered: ‎08-02-2007

回复: XDMA Credit mode, FIFO, …

credit is someting that used for the Flow control 

if the credit is run out the engineer will stop but will contiune when there is new buffer or credit available

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Visitor arminh
Visitor
376 Views
Registered: ‎03-25-2019

回复: XDMA Credit mode, FIFO, …

Ahh i did think that it would be like that.
Can i subtract from that credit value also while the engine is running?

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